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@@ -1107,3 +1107,170 @@ do { \
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/* BMIPS43xx */
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#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
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#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
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+
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+#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
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+#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
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+
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+#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
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+#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
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+
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+#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
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+#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
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+
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+#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
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+#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
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+
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+/* BMIPS5000 */
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+#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
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+#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
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+
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+#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
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+#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
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+
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+#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
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+#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
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+
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+#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
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+#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
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+
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+#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
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+#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
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+
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+#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
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+#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
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+
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+/*
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+ * Macros to access the floating point coprocessor control registers
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+ */
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+#define read_32bit_cp1_register(source) \
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+({ int __res; \
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+ __asm__ __volatile__( \
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+ ".set\tpush\n\t" \
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+ ".set\treorder\n\t" \
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+ /* gas fails to assemble cfc1 for some archs (octeon).*/ \
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+ ".set\tmips1\n\t" \
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+ "cfc1\t%0,"STR(source)"\n\t" \
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+ ".set\tpop" \
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+ : "=r" (__res)); \
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+ __res;})
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+
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+#define rddsp(mask) \
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+({ \
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+ unsigned int __res; \
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+ \
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+ __asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " # rddsp $1, %x1 \n" \
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+ " .word 0x7c000cb8 | (%x1 << 16) \n" \
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+ " move %0, $1 \n" \
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+ " .set pop \n" \
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+ : "=r" (__res) \
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+ : "i" (mask)); \
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+ __res; \
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+})
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+
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+#define wrdsp(val, mask) \
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+do { \
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+ __asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " move $1, %0 \n" \
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+ " # wrdsp $1, %x1 \n" \
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+ " .word 0x7c2004f8 | (%x1 << 11) \n" \
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+ " .set pop \n" \
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+ : \
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+ : "r" (val), "i" (mask)); \
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+} while (0)
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+
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+#if 0 /* Need DSP ASE capable assembler ... */
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+#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
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+#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
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+#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
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+#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
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+
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+#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
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+#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
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+#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
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+#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
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+
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+#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
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+#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
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+#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
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+#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
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+
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+#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
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+#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
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+#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
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+#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
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+
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+#else
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+
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+#define mfhi0() \
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+({ \
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+ unsigned long __treg; \
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+ \
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+ __asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " # mfhi %0, $ac0 \n" \
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+ " .word 0x00000810 \n" \
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+ " move %0, $1 \n" \
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+ " .set pop \n" \
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+ : "=r" (__treg)); \
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+ __treg; \
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+})
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+
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+#define mfhi1() \
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+({ \
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+ unsigned long __treg; \
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+ \
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+ __asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " # mfhi %0, $ac1 \n" \
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+ " .word 0x00200810 \n" \
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+ " move %0, $1 \n" \
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+ " .set pop \n" \
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+ : "=r" (__treg)); \
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+ __treg; \
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+})
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+
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+#define mfhi2() \
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+({ \
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+ unsigned long __treg; \
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+ \
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+ __asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " # mfhi %0, $ac2 \n" \
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+ " .word 0x00400810 \n" \
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+ " move %0, $1 \n" \
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+ " .set pop \n" \
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+ : "=r" (__treg)); \
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+ __treg; \
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+})
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+
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+#define mfhi3() \
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+({ \
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+ unsigned long __treg; \
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+ \
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+ __asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " # mfhi %0, $ac3 \n" \
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+ " .word 0x00600810 \n" \
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+ " move %0, $1 \n" \
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+ " .set pop \n" \
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+ : "=r" (__treg)); \
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+ __treg; \
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+})
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+
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+#define mflo0() \
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+({ \
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+ unsigned long __treg; \
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+ \
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+ __asm__ __volatile__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " # mflo %0, $ac0 \n" \
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李欣儒