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@@ -0,0 +1,98 @@
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+#ifndef __ALPHA_CIA__H__
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+#define __ALPHA_CIA__H__
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+
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+/* Define to experiment with fitting everything into one 512MB HAE window. */
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+#define CIA_ONE_HAE_WINDOW 1
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+
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+#include <linux/types.h>
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+#include <asm/compiler.h>
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+
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+/*
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+ * CIA is the internal name for the 21171 chipset which provides
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+ * memory controller and PCI access for the 21164 chip based systems.
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+ * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
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+ *
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+ * The lineage is a bit confused, since the 21174 was reportedly started
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+ * from the 21171 Pass 1 mask, and so is missing bug fixes that appear
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+ * in 21171 Pass 2 and 21172, but it also contains additional features.
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+ *
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+ * This file is based on:
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+ *
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+ * DECchip 21171 Core Logic Chipset
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+ * Technical Reference Manual
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+ *
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+ * EC-QE18B-TE
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+ *
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+ * david.rusling@reo.mts.dec.com Initial Version.
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+ *
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+ */
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+
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+/*
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+ * CIA ADDRESS BIT DEFINITIONS
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+ *
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+ * 3333 3333 3322 2222 2222 1111 1111 11
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+ * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
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+ * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
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+ * 1 000
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+ * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
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+ * | |\|
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+ * | Byte Enable --+ |
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+ * | Transfer Length --+
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+ * +-- IO space, not cached
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+ *
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+ * Byte Transfer
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+ * Enable Length Transfer Byte Address
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+ * adr<6:5> adr<4:3> Length Enable Adder
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+ * ---------------------------------------------
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+ * 00 00 Byte 1110 0x000
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+ * 01 00 Byte 1101 0x020
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+ * 10 00 Byte 1011 0x040
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+ * 11 00 Byte 0111 0x060
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+ *
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+ * 00 01 Word 1100 0x008
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+ * 01 01 Word 1001 0x028 <= Not supported in this code.
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+ * 10 01 Word 0011 0x048
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+ *
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+ * 00 10 Tribyte 1000 0x010
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+ * 01 10 Tribyte 0001 0x030
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+ *
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+ * 10 11 Longword 0000 0x058
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+ *
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+ * Note that byte enables are asserted low.
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+ *
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+ */
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+
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+#define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
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+#define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
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+#define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
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+
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+/*
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+ * 21171-CA Control and Status Registers
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+ */
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+#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
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+# define CIA_REV_MASK 0xff
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+#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
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+#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
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+# define CIA_CTRL_PCI_EN (1 << 0)
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+# define CIA_CTRL_PCI_LOCK_EN (1 << 1)
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+# define CIA_CTRL_PCI_LOOP_EN (1 << 2)
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+# define CIA_CTRL_FST_BB_EN (1 << 3)
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+# define CIA_CTRL_PCI_MST_EN (1 << 4)
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+# define CIA_CTRL_PCI_MEM_EN (1 << 5)
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+# define CIA_CTRL_PCI_REQ64_EN (1 << 6)
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+# define CIA_CTRL_PCI_ACK64_EN (1 << 7)
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+# define CIA_CTRL_ADDR_PE_EN (1 << 8)
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+# define CIA_CTRL_PERR_EN (1 << 9)
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+# define CIA_CTRL_FILL_ERR_EN (1 << 10)
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+# define CIA_CTRL_MCHK_ERR_EN (1 << 11)
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+# define CIA_CTRL_ECC_CHK_EN (1 << 12)
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+# define CIA_CTRL_ASSERT_IDLE_BC (1 << 13)
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+# define CIA_CTRL_COM_IDLE_BC (1 << 14)
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+# define CIA_CTRL_CSR_IOA_BYPASS (1 << 15)
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+# define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16)
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+# define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17)
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+# define CIA_CTRL_ARB_CPU_EN (1 << 18)
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+# define CIA_CTRL_EN_ARB_LINK (1 << 19)
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+# define CIA_CTRL_RD_TYPE_SHIFT 20
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+# define CIA_CTRL_RL_TYPE_SHIFT 24
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+# define CIA_CTRL_RM_TYPE_SHIFT 28
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