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+/*
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+ * Copyright 2005-2010 Analog Devices Inc.
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+ *
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+ * Licensed under the GPL-2 or later.
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+ */
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+
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+#ifndef _CDEF_BF561_H
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+#define _CDEF_BF561_H
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+
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+/*********************************************************************************** */
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+/* System MMR Register Map */
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+/*********************************************************************************** */
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+
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+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
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+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
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+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
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+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
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+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
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+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
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+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
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+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
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+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
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+#define bfin_read_CHIPID() bfin_read32(CHIPID)
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+
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+/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
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+#define bfin_read_SWRST() bfin_read16(SWRST)
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+#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
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+#define bfin_read_SYSCR() bfin_read16(SYSCR)
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+#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
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+#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
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+#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
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+#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
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+#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
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+#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
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+#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
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+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
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+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
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+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
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+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
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+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
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+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
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+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
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+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
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+#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
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+#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
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+#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
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+#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
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+#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
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+#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
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+#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
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+#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
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+#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
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+#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
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+#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
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+#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
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+#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
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+#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
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+#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
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+#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
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+
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+/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
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+#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
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+#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
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+#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
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+#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
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+#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
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+#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
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+#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
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+#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
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+#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
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+#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
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+#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
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+#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
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+#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
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+#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
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+#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
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+#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
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+#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
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+#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
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+#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
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+#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
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+#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
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+#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
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+#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
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+#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
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+#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
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+#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
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+#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
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+#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
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+#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
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+#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
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+#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
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+#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
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+#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
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+#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
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+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
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+#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
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+#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
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+#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
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+#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
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+#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
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+#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
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+
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+/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
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+#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
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+#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
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+#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
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+#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
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+#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
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+#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
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+
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+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
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+#define bfin_read_UART_THR() bfin_read16(UART_THR)
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+#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
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+#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
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+#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
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+#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
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+#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
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+#define bfin_read_UART_IER() bfin_read16(UART_IER)
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+#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
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+#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
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+#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
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+#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
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+#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
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+#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
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+#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
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+#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
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+#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
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+#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
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+#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
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+#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
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+#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
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+#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
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+#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
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+#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
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+#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
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+
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+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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+#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
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+#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
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+#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
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+#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
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+#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
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+#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
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+#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
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+#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
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+#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
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+#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
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+#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
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+#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
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+#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
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+#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
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+
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+/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
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+#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
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+#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
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+#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
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+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
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+#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
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+#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
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+#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
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+#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
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+#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
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+#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
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+#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
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+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
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+#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
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+#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
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+#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
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袁明明