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+/*
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+ * Copyright 2008-2010 Analog Devices Inc.
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+ *
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+ * Licensed under the GPL-2 or later.
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+ */
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+
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+#ifndef _CDEF_BF547_H
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+#define _CDEF_BF547_H
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+
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+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
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+#include "cdefBF54x_base.h"
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+
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+/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
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+
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+/* Timer Registers */
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+
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+#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
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+#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
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+#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
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+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
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+#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
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+#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
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+#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
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+#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
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+#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
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+#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
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+#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
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+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
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+#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
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+#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
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+#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
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+#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
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+#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
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+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
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+#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
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+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
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+#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
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+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
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+#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
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+#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
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+
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+/* Timer Groubfin_read_() of 3 */
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+
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+#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
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+#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
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+#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
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+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
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+#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
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+#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
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+
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+/* SPORT0 Registers */
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+
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+#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
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+#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
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+#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
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+#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
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+#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
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+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
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+#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
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+#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
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+#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
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+#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
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+#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
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+#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
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+#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
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+#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
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+#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
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+#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
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+#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
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+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
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+#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
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+#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
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+#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
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+#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
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+#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
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+#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
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+#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
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+#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
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+#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
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+#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
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+#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
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+#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
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+#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
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+#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
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+#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
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+#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
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+#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
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+#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
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+#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
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+#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
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+#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
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+#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
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+#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
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+#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
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+#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
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+#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
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+
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+/* EPPI0 Registers */
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+
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+#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
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+#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
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+#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
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+#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
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+#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
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+#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
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+#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
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+#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
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+#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
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+#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
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+#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
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+#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
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+#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
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+#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
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+#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
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+#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
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+#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
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+#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
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+#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
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+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
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+#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
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+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
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+#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
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+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
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+#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
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+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
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+#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
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+#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
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+
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+/* UART2 Registers */
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+
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+#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
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+#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
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+#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
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+#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
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+#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
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+#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
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