|
|
@@ -3215,3 +3215,67 @@ DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
|
|
|
*/
|
|
|
static struct omap_clk omap3xxx_clks[] = {
|
|
|
CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
|
|
|
+ CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
|
|
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
|
|
|
+ CLK("twl", "fck", &osc_sys_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
|
|
|
+ CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
|
|
|
+ CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
|
|
|
+ CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
|
|
|
+ CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "core_ck", &core_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
|
|
|
+ CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
|
|
|
+ CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
|
|
|
+ CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
|
|
+ CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
|
|
|
+ CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
|
|
|
+ CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
|
|
|
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
|
|
|
+ CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
|
|
|
+ CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
|
|
|
+ CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
|
|
|
+ CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
|
|
|
+ CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
|
|
|
+ CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
|
|
|
+ CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
|
|
|
+ CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
|
|
|
+ CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
|
|
|
+ CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
|
韩正义