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@@ -1037,3 +1037,96 @@ static struct clksrc_clk clk_sclk_spi0 = {
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.name = "sclk_spi",
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.devname = "s5pv210-spi.0",
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.enable = s5pv210_clk_mask0_ctrl,
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+ .ctrlbit = (1 << 16),
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+ },
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+ .sources = &clkset_group2,
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+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
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+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
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+ };
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+
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+static struct clksrc_clk clk_sclk_spi1 = {
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+ .clk = {
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+ .name = "sclk_spi",
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+ .devname = "s5pv210-spi.1",
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+ .enable = s5pv210_clk_mask0_ctrl,
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+ .ctrlbit = (1 << 17),
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+ },
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+ .sources = &clkset_group2,
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+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
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+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
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+ };
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+
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+
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+static struct clksrc_clk *clksrc_cdev[] = {
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+ &clk_sclk_uart0,
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+ &clk_sclk_uart1,
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+ &clk_sclk_uart2,
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+ &clk_sclk_uart3,
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+ &clk_sclk_mmc0,
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+ &clk_sclk_mmc1,
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+ &clk_sclk_mmc2,
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+ &clk_sclk_mmc3,
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+ &clk_sclk_spi0,
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+ &clk_sclk_spi1,
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+};
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+
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+static struct clk *clk_cdev[] = {
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+ &clk_hsmmc0,
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+ &clk_hsmmc1,
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+ &clk_hsmmc2,
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+ &clk_hsmmc3,
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+};
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+
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+/* Clock initialisation code */
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+static struct clksrc_clk *sysclks[] = {
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+ &clk_mout_apll,
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+ &clk_mout_epll,
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+ &clk_mout_mpll,
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+ &clk_armclk,
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+ &clk_hclk_msys,
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+ &clk_sclk_a2m,
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+ &clk_hclk_dsys,
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+ &clk_hclk_psys,
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+ &clk_pclk_msys,
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+ &clk_pclk_dsys,
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+ &clk_pclk_psys,
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+ &clk_vpllsrc,
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+ &clk_sclk_vpll,
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+ &clk_mout_dmc0,
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+ &clk_sclk_dmc0,
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+ &clk_sclk_audio0,
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+ &clk_sclk_audio1,
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+ &clk_sclk_audio2,
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+ &clk_sclk_spdif,
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+};
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+
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+static u32 epll_div[][6] = {
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+ { 48000000, 0, 48, 3, 3, 0 },
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+ { 96000000, 0, 48, 3, 2, 0 },
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+ { 144000000, 1, 72, 3, 2, 0 },
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+ { 192000000, 0, 48, 3, 1, 0 },
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+ { 288000000, 1, 72, 3, 1, 0 },
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+ { 32750000, 1, 65, 3, 4, 35127 },
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+ { 32768000, 1, 65, 3, 4, 35127 },
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+ { 45158400, 0, 45, 3, 3, 10355 },
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+ { 45000000, 0, 45, 3, 3, 10355 },
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+ { 45158000, 0, 45, 3, 3, 10355 },
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+ { 49125000, 0, 49, 3, 3, 9961 },
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+ { 49152000, 0, 49, 3, 3, 9961 },
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+ { 67737600, 1, 67, 3, 3, 48366 },
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+ { 67738000, 1, 67, 3, 3, 48366 },
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+ { 73800000, 1, 73, 3, 3, 47710 },
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+ { 73728000, 1, 73, 3, 3, 47710 },
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+ { 36000000, 1, 32, 3, 4, 0 },
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+ { 60000000, 1, 60, 3, 3, 0 },
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+ { 72000000, 1, 72, 3, 3, 0 },
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+ { 80000000, 1, 80, 3, 3, 0 },
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+ { 84000000, 0, 42, 3, 2, 0 },
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+ { 50000000, 0, 50, 3, 3, 0 },
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+};
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+
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+static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
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+{
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+ unsigned int epll_con, epll_con_k;
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+ unsigned int i;
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+
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徐寅秋