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@@ -305,3 +305,49 @@ union TPAchipAGPERR {
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#define TITAN_IACK_SC _TITAN_IACK_SC(0) /* hack! */
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/*
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+ * The canonical non-remaped I/O and MEM addresses have these values
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+ * subtracted out. This is arranged so that folks manipulating ISA
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+ * devices can use their familiar numbers and have them map to bus 0.
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+ */
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+
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+#define TITAN_IO_BIAS TITAN_IO(0)
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+#define TITAN_MEM_BIAS TITAN_MEM(0)
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+
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+/* The IO address space is larger than 0xffff */
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+#define TITAN_IO_SPACE (TITAN_CONF(0) - TITAN_IO(0))
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+
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+/* TIG Space */
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+#define TITAN_TIG_SPACE (TITAN_BASE + 0x100000000UL)
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+
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+/* Offset between ram physical addresses and pci64 DAC bus addresses. */
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+/* ??? Just a guess. Ought to confirm it hasn't been moved. */
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+#define TITAN_DAC_OFFSET (1UL << 40)
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+
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+/*
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+ * Data structure for handling TITAN machine checks:
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+ */
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+#define SCB_Q_SYSERR 0x620
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+#define SCB_Q_PROCERR 0x630
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+#define SCB_Q_SYSMCHK 0x660
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+#define SCB_Q_PROCMCHK 0x670
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+#define SCB_Q_SYSEVENT 0x680 /* environmental / system management */
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+struct el_TITAN_sysdata_mcheck {
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+ u64 summary; /* 0x00 */
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+ u64 c_dirx; /* 0x08 */
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+ u64 c_misc; /* 0x10 */
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+ u64 p0_serror; /* 0x18 */
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+ u64 p0_gperror; /* 0x20 */
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+ u64 p0_aperror; /* 0x28 */
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+ u64 p0_agperror;/* 0x30 */
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+ u64 p1_serror; /* 0x38 */
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+ u64 p1_gperror; /* 0x40 */
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+ u64 p1_aperror; /* 0x48 */
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+ u64 p1_agperror;/* 0x50 */
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+};
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+
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+/*
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+ * System area for a privateer 680 environmental/system management mcheck
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+ */
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+struct el_PRIVATEER_envdata_mcheck {
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+ u64 summary; /* 0x00 */
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+ u64 c_dirx; /* 0x08 */
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