|
|
@@ -190,3 +190,68 @@
|
|
|
#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
|
|
|
#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
|
|
|
#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
|
|
|
+#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
|
|
|
+#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
|
|
|
+#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
|
|
|
+#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
|
|
|
+#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
|
|
|
+#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
|
|
|
+#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
|
|
|
+#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
|
|
|
+#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
|
|
|
+
|
|
|
+#define UDCCN(x) __REG2(0x40600400, (x)<<2)
|
|
|
+#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
|
|
|
+#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
|
|
|
+#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
|
|
|
+#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
|
|
|
+#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
|
|
|
+#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
|
|
|
+#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
|
|
|
+#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
|
|
|
+#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
|
|
|
+#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
|
|
|
+#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
|
|
|
+#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
|
|
|
+#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
|
|
|
+#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
|
|
|
+#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
|
|
|
+#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
|
|
|
+#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
|
|
|
+#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
|
|
|
+#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
|
|
|
+#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
|
|
|
+#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
|
|
|
+#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
|
|
|
+#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
|
|
|
+
|
|
|
+#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
|
|
|
+#define UDCCONR_CN_S (25)
|
|
|
+#define UDCCONR_IN (0x07 << 22) /* Interface Number */
|
|
|
+#define UDCCONR_IN_S (22)
|
|
|
+#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
|
|
|
+#define UDCCONR_AISN_S (19)
|
|
|
+#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
|
|
|
+#define UDCCONR_EN_S (15)
|
|
|
+#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
|
|
|
+#define UDCCONR_ET_S (13)
|
|
|
+#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
|
|
|
+#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
|
|
|
+#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
|
|
|
+#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
|
|
|
+#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
|
|
|
+#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
|
|
|
+#define UDCCONR_MPS_S (2)
|
|
|
+#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
|
|
|
+#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
|
|
|
+
|
|
|
+
|
|
|
+#define UDC_INT_FIFOERROR (0x2)
|
|
|
+#define UDC_INT_PACKETCMP (0x1)
|
|
|
+
|
|
|
+#define UDC_FNR_MASK (0x7ff)
|
|
|
+
|
|
|
+#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
|
|
|
+#define UDC_BCR_MASK (0x3ff)
|
|
|
+
|
|
|
+#endif
|
姜征