efDataDiscreteRateMining calculationDeviationOfLeakageCurrent.c 张婷 commit at 2021-01-08

efDataDiscreteRateMining/standardDeviationCalculation/calculationDeviationOfLeakageCurrent.c

@@ -372,3 +372,128 @@ static void __init map_sa1100_gpio_regs( void )
 	*pmd = __pmd(phys | prot);
 	flush_pmd_entry(pmd);
 }
+
+/*
+ * Read System Configuration "Register"
+ * (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
+ * User's Guide", section 4.4.1)
+ *
+ * This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
+ * to set up the serial port for decompression status messages. We
+ * repeat it here because the kernel may not be loaded as a zImage, and
+ * also because it's a hassle to communicate the SCR value to the kernel
+ * from the decompressor.
+ *
+ * Note that IRQs are guaranteed to be disabled.
+ */
+static void __init get_assabet_scr(void)
+{
+	unsigned long uninitialized_var(scr), i;
+
+	GPDR |= 0x3fc;			/* Configure GPIO 9:2 as outputs */
+	GPSR = 0x3fc;			/* Write 0xFF to GPIO 9:2 */
+	GPDR &= ~(0x3fc);		/* Configure GPIO 9:2 as inputs */
+	for(i = 100; i--; )		/* Read GPIO 9:2 */
+		scr = GPLR;
+	GPDR |= 0x3fc;			/*  restore correct pin direction */
+	scr &= 0x3fc;			/* save as system configuration byte. */
+	SCR_value = scr;
+}
+
+static void __init
+fixup_assabet(struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+	/* This must be done before any call to machine_has_neponset() */
+	map_sa1100_gpio_regs();
+	get_assabet_scr();
+
+	if (machine_has_neponset())
+		printk("Neponset expansion board detected\n");
+}
+
+
+static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+	if (port->mapbase == _Ser1UTCR0) {
+		if (state)
+			ASSABET_BCR_clear(ASSABET_BCR_RS232EN |
+					  ASSABET_BCR_COM_RTS |
+					  ASSABET_BCR_COM_DTR);
+		else
+			ASSABET_BCR_set(ASSABET_BCR_RS232EN |
+					ASSABET_BCR_COM_RTS |
+					ASSABET_BCR_COM_DTR);
+	}
+}
+
+/*
+ * Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
+ * and UART3 (radio module).  We only handle them for UART1 here.
+ */
+static void assabet_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+	if (port->mapbase == _Ser1UTCR0) {
+		u_int set = 0, clear = 0;
+
+		if (mctrl & TIOCM_RTS)
+			clear |= ASSABET_BCR_COM_RTS;
+		else
+			set |= ASSABET_BCR_COM_RTS;
+
+		if (mctrl & TIOCM_DTR)
+			clear |= ASSABET_BCR_COM_DTR;
+		else
+			set |= ASSABET_BCR_COM_DTR;
+
+		ASSABET_BCR_clear(clear);
+		ASSABET_BCR_set(set);
+	}
+}
+
+static u_int assabet_get_mctrl(struct uart_port *port)
+{
+	u_int ret = 0;
+	u_int bsr = ASSABET_BSR;
+
+	/* need 2 reads to read current value */
+	bsr = ASSABET_BSR;
+
+	if (port->mapbase == _Ser1UTCR0) {
+		if (bsr & ASSABET_BSR_COM_DCD)
+			ret |= TIOCM_CD;
+		if (bsr & ASSABET_BSR_COM_CTS)
+			ret |= TIOCM_CTS;
+		if (bsr & ASSABET_BSR_COM_DSR)
+			ret |= TIOCM_DSR;
+	} else if (port->mapbase == _Ser3UTCR0) {
+		if (bsr & ASSABET_BSR_RAD_DCD)
+			ret |= TIOCM_CD;
+		if (bsr & ASSABET_BSR_RAD_CTS)
+			ret |= TIOCM_CTS;
+		if (bsr & ASSABET_BSR_RAD_DSR)
+			ret |= TIOCM_DSR;
+		if (bsr & ASSABET_BSR_RAD_RI)
+			ret |= TIOCM_RI;
+	} else {
+		ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
+	}
+
+	return ret;
+}
+
+static struct sa1100_port_fns assabet_port_fns __initdata = {
+	.set_mctrl	= assabet_set_mctrl,
+	.get_mctrl	= assabet_get_mctrl,
+	.pm		= assabet_uart_pm,
+};
+
+static struct map_desc assabet_io_desc[] __initdata = {
+  	{	/* Board Control Register */
+		.virtual	=  0xf1000000,
+		.pfn		= __phys_to_pfn(0x12000000),
+		.length		= 0x00100000,
+		.type		= MT_DEVICE
+	}, {	/* MQ200 */
+		.virtual	=  0xf2800000,
+		.pfn		= __phys_to_pfn(0x4b800000),
+		.length		= 0x00800000,