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@@ -213,3 +213,100 @@ typedef struct pal_cache_config_info_s {
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#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
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* back depending on TLB
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* memory attributes
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+ */
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+
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+
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+/* Possible values for cache hints */
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+
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+#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
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+#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
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+#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
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+
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+/* Processor cache protection information */
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+typedef union pal_cache_protection_element_u {
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+ u32 pcpi_data;
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+ struct {
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+ u32 data_bits : 8, /* # data bits covered by
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+ * each unit of protection
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+ */
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+
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+ tagprot_lsb : 6, /* Least -do- */
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+ tagprot_msb : 6, /* Most Sig. tag address
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+ * bit that this
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+ * protection covers.
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+ */
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+ prot_bits : 6, /* # of protection bits */
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+ method : 4, /* Protection method */
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+ t_d : 2; /* Indicates which part
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+ * of the cache this
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+ * protection encoding
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+ * applies.
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+ */
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+ } pcp_info;
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+} pal_cache_protection_element_t;
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+
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+#define pcpi_cache_prot_part pcp_info.t_d
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+#define pcpi_prot_method pcp_info.method
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+#define pcpi_prot_bits pcp_info.prot_bits
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+#define pcpi_tagprot_msb pcp_info.tagprot_msb
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+#define pcpi_tagprot_lsb pcp_info.tagprot_lsb
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+#define pcpi_data_bits pcp_info.data_bits
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+
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+/* Processor cache part encodings */
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+#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
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+#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
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+#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
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+ * more significant )
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+ */
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+#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
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+ * more significant )
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+ */
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+#define PAL_CACHE_PROT_PART_MAX 6
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+
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+
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+typedef struct pal_cache_protection_info_s {
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+ pal_status_t pcpi_status;
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+ pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
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+} pal_cache_protection_info_t;
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+
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+
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+/* Processor cache protection method encodings */
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+#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
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+#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
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+#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
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+#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
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+
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+
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+/* Processor cache line identification in the hierarchy */
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+typedef union pal_cache_line_id_u {
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+ u64 pclid_data;
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+ struct {
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+ u64 cache_type : 8, /* 7-0 cache type */
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+ level : 8, /* 15-8 level of the
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+ * cache in the
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+ * hierarchy.
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+ */
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+ way : 8, /* 23-16 way in the set
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+ */
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+ part : 8, /* 31-24 part of the
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+ * cache
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+ */
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+ reserved : 32; /* 63-32 is reserved*/
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+ } pclid_info_read;
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+ struct {
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+ u64 cache_type : 8, /* 7-0 cache type */
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+ level : 8, /* 15-8 level of the
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+ * cache in the
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+ * hierarchy.
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+ */
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+ way : 8, /* 23-16 way in the set
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+ */
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+ part : 8, /* 31-24 part of the
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+ * cache
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+ */
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+ mesi : 8, /* 39-32 cache line
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+ * state
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+ */
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+ start : 8, /* 47-40 lsb of data to
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+ * invert
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+ */
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