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@@ -2480,3 +2480,59 @@ DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
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DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
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static struct clk pka_ick;
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+
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+static const char *pka_ick_parent_names[] = {
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+ "security_l3_ick",
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+};
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+
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+static struct clk_hw_omap pka_ick_hw = {
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+ .hw = {
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+ .clk = &pka_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
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+ .enable_bit = OMAP3430_EN_PKA_SHIFT,
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+};
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+
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+DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
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+
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+DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
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+ OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
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+ OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
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+ CLK_DIVIDER_ONE_BASED, NULL);
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+
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+static struct clk rng_ick;
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+
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+static struct clk_hw_omap rng_ick_hw = {
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+ .hw = {
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+ .clk = &rng_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
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+ .enable_bit = OMAP3430_EN_RNG_SHIFT,
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+};
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+
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+DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
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+
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+static struct clk sad2d_ick;
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+
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+static struct clk_hw_omap sad2d_ick_hw = {
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+ .hw = {
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+ .clk = &sad2d_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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+ .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
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+ .clkdm_name = "d2d_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
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+
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+static struct clk sdrc_ick;
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+
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+static struct clk_hw_omap sdrc_ick_hw = {
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+ .hw = {
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+ .clk = &sdrc_ick,
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+ },
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+ .ops = &clkhwops_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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