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@@ -130,3 +130,58 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
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/* Read-modify-write a register in CM1. Caller must lock */
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u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
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+ s16 idx)
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+{
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+ u32 v;
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+
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+ v = omap4_cminst_read_inst_reg(part, inst, idx);
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+ v &= ~mask;
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+ v |= bits;
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+ omap4_cminst_write_inst_reg(v, part, inst, idx);
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+
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+ return v;
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+}
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+
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+u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
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+{
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+ return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
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+}
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+
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+u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
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+{
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+ return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
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+}
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+
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+u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
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+{
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+ u32 v;
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+
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+ v = omap4_cminst_read_inst_reg(part, inst, idx);
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+ v &= mask;
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+ v >>= __ffs(mask);
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+
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+ return v;
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+}
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+
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+/*
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+ *
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+ */
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+
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+/**
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+ * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
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+ * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
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+ * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
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+ * @inst: CM instance register offset (*_INST macro)
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+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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+ *
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+ * @c must be the unshifted value for CLKTRCTRL - i.e., this function
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+ * will handle the shift itself.
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+ */
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+static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
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+{
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+ u32 v;
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+
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+ v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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+ v &= ~OMAP4430_CLKTRCTRL_MASK;
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+ v |= c << OMAP4430_CLKTRCTRL_SHIFT;
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+ omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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