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@@ -97,3 +97,142 @@
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/* Memory regions and CS */
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#define MX27_SDRAM_BASE_ADDR 0xa0000000
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#define MX27_CSD1_BASE_ADDR 0xb0000000
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+
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+#define MX27_CS0_BASE_ADDR 0xc0000000
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+#define MX27_CS1_BASE_ADDR 0xc8000000
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+#define MX27_CS2_BASE_ADDR 0xd0000000
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+#define MX27_CS3_BASE_ADDR 0xd2000000
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+#define MX27_CS4_BASE_ADDR 0xd4000000
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+#define MX27_CS5_BASE_ADDR 0xd6000000
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+
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+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
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+#define MX27_X_MEMC_BASE_ADDR 0xd8000000
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+#define MX27_X_MEMC_SIZE SZ_1M
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+#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
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+#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
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+#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
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+#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
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+#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
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+
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+#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
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+#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
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+#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
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+#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
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+
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+#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
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+
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+/* IRAM */
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+#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
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+
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+#define MX27_IO_P2V(x) IMX_IO_P2V(x)
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+#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
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+
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+/* fixed interrupt numbers */
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+#include <asm/irq.h>
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+#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
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+#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
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+#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
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+#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
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+#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
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+#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
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+#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
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+#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
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+#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
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+#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
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+#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
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+#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
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+#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
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+#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
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+#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
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+#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
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+#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
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+#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
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+#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
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+#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
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+#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
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+#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
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+#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
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+#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
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+#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
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+#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
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+#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
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+#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
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+#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
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+#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
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+#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
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+#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
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+#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
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+#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
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+#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
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+#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
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+#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
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+#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
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+#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
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+#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
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+#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
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+#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
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+#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
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+#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
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+#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
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+#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
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+#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
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+#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
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+#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
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+#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
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+#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
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+#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
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+#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
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+#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
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+#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
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+#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
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+#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
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+#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
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+#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
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+#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
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+#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
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+#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
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+#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
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+
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+/* fixed DMA request numbers */
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+#define MX27_DMA_REQ_CSPI3_RX 1
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+#define MX27_DMA_REQ_CSPI3_TX 2
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+#define MX27_DMA_REQ_EXT 3
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+#define MX27_DMA_REQ_MSHC 4
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+#define MX27_DMA_REQ_SDHC2 6
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+#define MX27_DMA_REQ_SDHC1 7
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+#define MX27_DMA_REQ_SSI2_RX0 8
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+#define MX27_DMA_REQ_SSI2_TX0 9
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+#define MX27_DMA_REQ_SSI2_RX1 10
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+#define MX27_DMA_REQ_SSI2_TX1 11
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+#define MX27_DMA_REQ_SSI1_RX0 12
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+#define MX27_DMA_REQ_SSI1_TX0 13
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+#define MX27_DMA_REQ_SSI1_RX1 14
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+#define MX27_DMA_REQ_SSI1_TX1 15
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+#define MX27_DMA_REQ_CSPI2_RX 16
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+#define MX27_DMA_REQ_CSPI2_TX 17
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+#define MX27_DMA_REQ_CSPI1_RX 18
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+#define MX27_DMA_REQ_CSPI1_TX 19
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+#define MX27_DMA_REQ_UART4_RX 20
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+#define MX27_DMA_REQ_UART4_TX 21
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+#define MX27_DMA_REQ_UART3_RX 22
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+#define MX27_DMA_REQ_UART3_TX 23
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+#define MX27_DMA_REQ_UART2_RX 24
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+#define MX27_DMA_REQ_UART2_TX 25
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+#define MX27_DMA_REQ_UART1_RX 26
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+#define MX27_DMA_REQ_UART1_TX 27
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+#define MX27_DMA_REQ_ATA_TX 28
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+#define MX27_DMA_REQ_ATA_RCV 29
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+#define MX27_DMA_REQ_CSI_STAT 30
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+#define MX27_DMA_REQ_CSI_RX 31
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+#define MX27_DMA_REQ_UART5_TX 32
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+#define MX27_DMA_REQ_UART5_RX 33
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+#define MX27_DMA_REQ_UART6_TX 34
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+#define MX27_DMA_REQ_UART6_RX 35
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+#define MX27_DMA_REQ_SDHC3 36
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+#define MX27_DMA_REQ_NFC 37
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+
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+#ifndef __ASSEMBLY__
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+extern int mx27_revision(void);
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+#endif
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+
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+#endif /* ifndef __MACH_MX27_H__ */
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