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@@ -1212,3 +1212,187 @@
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#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
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#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
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#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
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+#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
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+#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
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+
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+#define GPDR_In 0 /* Input */
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+#define GPDR_Out 1 /* Output */
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+
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+
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+/*
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+ * Interrupt Controller (IC) control registers
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+ *
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+ * Registers
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+ * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
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+ * Pending register (read).
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+ * ICMR Interrupt Controller (IC) Mask Register (read/write).
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+ * ICLR Interrupt Controller (IC) Level Register (read/write).
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+ * ICCR Interrupt Controller (IC) Control Register
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+ * (read/write).
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+ * [The ICCR register is only implemented in versions 2.0
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+ * (rev. = 8) and higher of the StrongARM SA-1100.]
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+ * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
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+ * (FIQ) Pending register (read).
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+ * ICPR Interrupt Controller (IC) Pending Register (read).
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+ * [The ICPR register is active low (inverted) in
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+ * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
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+ * StrongARM SA-1100, it is active high (non-inverted) in
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+ * versions 2.0 (rev. = 8) and higher.]
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+ */
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+
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+#define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
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+#define ICMR __REG(0x90050004) /* IC Mask Reg. */
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+#define ICLR __REG(0x90050008) /* IC Level Reg. */
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+#define ICCR __REG(0x9005000C) /* IC Control Reg. */
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+#define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
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+#define ICPR __REG(0x90050020) /* IC Pending Reg. */
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+
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+#define IC_GPIO(Nb) /* GPIO [0..10] */ \
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+ (0x00000001 << (Nb))
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+#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
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+#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
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+#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
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+#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
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+#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
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+#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
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+#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
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+#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
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+#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
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+#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
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+#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
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+#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
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+#define IC_LCD 0x00001000 /* LCD controller */
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+#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
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+#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
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+#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
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+#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
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+#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
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+#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
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+#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
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+#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
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+ (0x00100000 << (Nb))
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+#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
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+#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
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+#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
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+#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
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+#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
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+#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
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+#define IC_OST(Nb) /* OS Timer match [0..3] */ \
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+ (0x04000000 << (Nb))
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+#define IC_OST0 IC_OST (0) /* OS Timer match 0 */
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+#define IC_OST1 IC_OST (1) /* OS Timer match 1 */
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+#define IC_OST2 IC_OST (2) /* OS Timer match 2 */
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+#define IC_OST3 IC_OST (3) /* OS Timer match 3 */
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+#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
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+#define IC_RTCAlrm 0x80000000 /* RTC Alarm */
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+
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+#define ICLR_IRQ 0 /* Interrupt ReQuest */
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+#define ICLR_FIQ 1 /* Fast Interrupt reQuest */
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+
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+#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
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+ /* Mask */
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+#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
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+ /* (ICMR ignored) */
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+#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
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+ /* enable (ICMR used) */
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+
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+
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+/*
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+ * Peripheral Pin Controller (PPC) control registers
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+ *
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+ * Registers
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+ * PPDR Peripheral Pin Controller (PPC) Pin Direction
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+ * Register (read/write).
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+ * PPSR Peripheral Pin Controller (PPC) Pin State Register
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+ * (read/write).
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+ * PPAR Peripheral Pin Controller (PPC) Pin Assignment
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+ * Register (read/write).
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+ * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
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+ * Direction Register (read/write).
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+ * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
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+ * (read).
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+ */
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+
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+#define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
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+#define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
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+#define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
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+#define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
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+#define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
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+
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+#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
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+ (0x00000001 << (Nb))
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+#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
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+#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
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+#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
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+#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
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+#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
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+#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
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+#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
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+#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
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+#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
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+#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
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+#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
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+#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
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+ /* ser. port 1: */
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+#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
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+#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
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+ /* ser. port 2: */
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+#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
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+#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
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+ /* ser. port 3: */
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+#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
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+#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
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+ /* ser. port 4: */
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+#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
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+#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
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+#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
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+#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
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+
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+#define PPDR_In 0 /* Input */
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+#define PPDR_Out 1 /* Output */
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+
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+ /* ser. port 1: */
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+#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
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+#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
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+#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
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+ /* ser. port 4: */
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+#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
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+#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
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+ /* & SFRM_C */
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+#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
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+
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+#define PSDR_OutL 0 /* Output Low in sleep mode */
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+#define PSDR_Flt 1 /* Floating (input) in sleep mode */
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+
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+#define PPFR_LCD 0x00000001 /* LCD controller */
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+#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
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+#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
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+#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
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+#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
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+#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
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+#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
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+#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
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+#define PPFR_PerEn 0 /* Peripheral Enabled */
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+#define PPFR_PPCEn 1 /* PPC Enabled */
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+
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+
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+/*
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+ * Dynamic Random-Access Memory (DRAM) control registers
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+ *
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+ * Registers
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+ * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
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+ * CoNFiGuration register (read/write).
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+ * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
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+ * Column Address Strobe (CAS) shift register 0
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+ * (read/write).
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+ * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
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+ * Column Address Strobe (CAS) shift register 1
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+ * (read/write).
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+ * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
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+ * Column Address Strobe (CAS) shift register 2
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+ * (read/write).
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+ *
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+ * Clocks
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+ * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
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+ * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
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+ * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
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沈瑞清