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@@ -143,3 +143,117 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
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chip->irq_eoi(&desc->irq_data);
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chip->irq_unmask(&desc->irq_data);
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+ prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
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+}
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+
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+/* Public functions */
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+
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+/**
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+ * omap_prcm_event_to_irq - given a PRCM event name, returns the
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+ * corresponding IRQ on which the handler should be registered
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+ * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
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+ *
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+ * Returns the Linux internal IRQ ID corresponding to @name upon success,
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+ * or -ENOENT upon failure.
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+ */
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+int omap_prcm_event_to_irq(const char *name)
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+{
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+ int i;
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+
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+ if (!prcm_irq_setup || !name)
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+ return -ENOENT;
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+
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+ for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
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+ if (!strcmp(prcm_irq_setup->irqs[i].name, name))
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+ return prcm_irq_setup->base_irq +
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+ prcm_irq_setup->irqs[i].offset;
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+
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+ return -ENOENT;
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+}
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+
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+/**
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+ * omap_prcm_irq_cleanup - reverses memory allocated and other steps
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+ * done by omap_prcm_register_chain_handler()
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+ *
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+ * No return value.
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+ */
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+void omap_prcm_irq_cleanup(void)
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+{
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+ int i;
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+
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+ if (!prcm_irq_setup) {
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+ pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
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+ return;
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+ }
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+
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+ if (prcm_irq_chips) {
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+ for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
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+ if (prcm_irq_chips[i])
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+ irq_remove_generic_chip(prcm_irq_chips[i],
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+ 0xffffffff, 0, 0);
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+ prcm_irq_chips[i] = NULL;
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+ }
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+ kfree(prcm_irq_chips);
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+ prcm_irq_chips = NULL;
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+ }
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+
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+ kfree(prcm_irq_setup->saved_mask);
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+ prcm_irq_setup->saved_mask = NULL;
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+
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+ kfree(prcm_irq_setup->priority_mask);
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+ prcm_irq_setup->priority_mask = NULL;
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+
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+ irq_set_chained_handler(prcm_irq_setup->irq, NULL);
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+
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+ if (prcm_irq_setup->base_irq > 0)
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+ irq_free_descs(prcm_irq_setup->base_irq,
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+ prcm_irq_setup->nr_regs * 32);
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+ prcm_irq_setup->base_irq = 0;
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+}
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+
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+void omap_prcm_irq_prepare(void)
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+{
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+ prcm_irq_setup->suspended = true;
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+}
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+
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+void omap_prcm_irq_complete(void)
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+{
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+ prcm_irq_setup->suspended = false;
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+
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+ /* If we have not saved the masks, do not attempt to restore */
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+ if (!prcm_irq_setup->suspend_save_flag)
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+ return;
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+
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+ prcm_irq_setup->suspend_save_flag = false;
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+
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+ /*
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+ * Re-enable all masked PRCM irq sources, this causes the PRCM
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+ * interrupt to fire immediately if the events were masked
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+ * previously in the chain handler
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+ */
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+ prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
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+}
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+
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+/**
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+ * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
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+ * handler based on provided parameters
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+ * @irq_setup: hardware data about the underlying PRM/PRCM
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+ *
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+ * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
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+ * one generic IRQ chip per PRM interrupt status/enable register pair.
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+ * Returns 0 upon success, -EINVAL if called twice or if invalid
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+ * arguments are passed, or -ENOMEM on any other error.
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+ */
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+int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
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+{
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+ int nr_regs;
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+ u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
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+ int offset, i;
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+ struct irq_chip_generic *gc;
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+ struct irq_chip_type *ct;
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+
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+ if (!irq_setup)
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+ return -EINVAL;
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+
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+ nr_regs = irq_setup->nr_regs;
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+
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韩正义