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@@ -1821,3 +1821,186 @@
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#define CB3WCOUNT 0x8 /* Clear write count 3 */
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#define CB4WCOUNT 0x10 /* Clear write count 4 */
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#define CB5WCOUNT 0x20 /* Clear write count 5 */
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+#define CB6WCOUNT 0x40 /* Clear write count 6 */
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+#define CB7WCOUNT 0x80 /* Clear write count 7 */
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+#define CBRCOUNT 0x100 /* Clear read count 0 */
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+#define CB1RCOUNT 0x200 /* Clear read count 1 */
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+#define CB2RCOUNT 0x400 /* Clear read count 2 */
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+#define CB3RCOUNT 0x800 /* Clear read count 3 */
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+#define CB4RCOUNT 0x1000 /* Clear read count 4 */
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+#define CB5RCOUNT 0x2000 /* Clear read count 5 */
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+#define CB6RCOUNT 0x4000 /* Clear read count 6 */
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+#define CB7RCOUNT 0x8000 /* Clear read count 7 */
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+#define CRACOUNT 0x10000 /* Clear row activation count */
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+#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
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+#define CARCOUNT 0x40000 /* Clear auto-refresh count */
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+#define CG0COUNT 0x100000 /* Clear grant count 0 */
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+#define CG1COUNT 0x200000 /* Clear grant count 1 */
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+#define CG2COUNT 0x400000 /* Clear grant count 2 */
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+#define CG3COUNT 0x800000 /* Clear grant count 3 */
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+
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+/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
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+
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+#define Px0 0x1 /* GPIO 0 */
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+#define Px1 0x2 /* GPIO 1 */
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+#define Px2 0x4 /* GPIO 2 */
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+#define Px3 0x8 /* GPIO 3 */
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+#define Px4 0x10 /* GPIO 4 */
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+#define Px5 0x20 /* GPIO 5 */
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+#define Px6 0x40 /* GPIO 6 */
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+#define Px7 0x80 /* GPIO 7 */
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+#define Px8 0x100 /* GPIO 8 */
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+#define Px9 0x200 /* GPIO 9 */
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+#define Px10 0x400 /* GPIO 10 */
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+#define Px11 0x800 /* GPIO 11 */
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+#define Px12 0x1000 /* GPIO 12 */
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+#define Px13 0x2000 /* GPIO 13 */
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+#define Px14 0x4000 /* GPIO 14 */
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+#define Px15 0x8000 /* GPIO 15 */
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+
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+/* Bit masks for PORTA_MUX - PORTJ_MUX */
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+
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+#define PxM0 0x3 /* GPIO Mux 0 */
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+#define PxM1 0xc /* GPIO Mux 1 */
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+#define PxM2 0x30 /* GPIO Mux 2 */
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+#define PxM3 0xc0 /* GPIO Mux 3 */
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+#define PxM4 0x300 /* GPIO Mux 4 */
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+#define PxM5 0xc00 /* GPIO Mux 5 */
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+#define PxM6 0x3000 /* GPIO Mux 6 */
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+#define PxM7 0xc000 /* GPIO Mux 7 */
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+#define PxM8 0x30000 /* GPIO Mux 8 */
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+#define PxM9 0xc0000 /* GPIO Mux 9 */
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+#define PxM10 0x300000 /* GPIO Mux 10 */
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+#define PxM11 0xc00000 /* GPIO Mux 11 */
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+#define PxM12 0x3000000 /* GPIO Mux 12 */
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+#define PxM13 0xc000000 /* GPIO Mux 13 */
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+#define PxM14 0x30000000 /* GPIO Mux 14 */
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+#define PxM15 0xc0000000 /* GPIO Mux 15 */
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+
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+
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+/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
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+
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+#define IB0 0x1 /* Interrupt Bit 0 */
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+#define IB1 0x2 /* Interrupt Bit 1 */
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+#define IB2 0x4 /* Interrupt Bit 2 */
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+#define IB3 0x8 /* Interrupt Bit 3 */
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+#define IB4 0x10 /* Interrupt Bit 4 */
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+#define IB5 0x20 /* Interrupt Bit 5 */
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+#define IB6 0x40 /* Interrupt Bit 6 */
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+#define IB7 0x80 /* Interrupt Bit 7 */
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+#define IB8 0x100 /* Interrupt Bit 8 */
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+#define IB9 0x200 /* Interrupt Bit 9 */
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+#define IB10 0x400 /* Interrupt Bit 10 */
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+#define IB11 0x800 /* Interrupt Bit 11 */
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+#define IB12 0x1000 /* Interrupt Bit 12 */
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+#define IB13 0x2000 /* Interrupt Bit 13 */
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+#define IB14 0x4000 /* Interrupt Bit 14 */
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+#define IB15 0x8000 /* Interrupt Bit 15 */
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+
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+/* Bit masks for TIMERx_CONFIG */
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+
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+#define TMODE 0x3 /* Timer Mode */
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+#define PULSE_HI 0x4 /* Pulse Polarity */
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+#define PERIOD_CNT 0x8 /* Period Count */
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+#define IRQ_ENA 0x10 /* Interrupt Request Enable */
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+#define TIN_SEL 0x20 /* Timer Input Select */
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+#define OUT_DIS 0x40 /* Output Pad Disable */
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+#define CLK_SEL 0x80 /* Timer Clock Select */
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+#define TOGGLE_HI 0x100 /* Toggle Mode */
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+#define EMU_RUN 0x200 /* Emulation Behavior Select */
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+#define ERR_TYP 0xc000 /* Error Type */
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+
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+/* Bit masks for TIMER_ENABLE0 */
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+
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+#define TIMEN0 0x1 /* Timer 0 Enable */
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+#define TIMEN1 0x2 /* Timer 1 Enable */
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+#define TIMEN2 0x4 /* Timer 2 Enable */
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+#define TIMEN3 0x8 /* Timer 3 Enable */
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+#define TIMEN4 0x10 /* Timer 4 Enable */
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+#define TIMEN5 0x20 /* Timer 5 Enable */
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+#define TIMEN6 0x40 /* Timer 6 Enable */
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+#define TIMEN7 0x80 /* Timer 7 Enable */
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+
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+/* Bit masks for TIMER_DISABLE0 */
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+
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+#define TIMDIS0 0x1 /* Timer 0 Disable */
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+#define TIMDIS1 0x2 /* Timer 1 Disable */
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+#define TIMDIS2 0x4 /* Timer 2 Disable */
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+#define TIMDIS3 0x8 /* Timer 3 Disable */
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+#define TIMDIS4 0x10 /* Timer 4 Disable */
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+#define TIMDIS5 0x20 /* Timer 5 Disable */
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+#define TIMDIS6 0x40 /* Timer 6 Disable */
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+#define TIMDIS7 0x80 /* Timer 7 Disable */
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+
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+/* Bit masks for TIMER_STATUS0 */
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+
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+#define TIMIL0 0x1 /* Timer 0 Interrupt */
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+#define TIMIL1 0x2 /* Timer 1 Interrupt */
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+#define TIMIL2 0x4 /* Timer 2 Interrupt */
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+#define TIMIL3 0x8 /* Timer 3 Interrupt */
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+#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
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+#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
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+#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
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+#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
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+#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
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+#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
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+#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
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+#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
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+#define TIMIL4 0x10000 /* Timer 4 Interrupt */
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+#define TIMIL5 0x20000 /* Timer 5 Interrupt */
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+#define TIMIL6 0x40000 /* Timer 6 Interrupt */
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+#define TIMIL7 0x80000 /* Timer 7 Interrupt */
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+#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
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+#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
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+#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
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+#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
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+#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
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+#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
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+#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
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+#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
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+
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+/* Bit masks for SECURE_SYSSWT */
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+
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+#define EMUDABL 0x1 /* Emulation Disable. */
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+#define RSTDABL 0x2 /* Reset Disable */
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+#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
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+#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
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+#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
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+#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
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+#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
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+#define EMUOVR 0x4000 /* Emulation Override */
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+#define OTPSEN 0x8000 /* OTP Secrets Enable. */
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+#define L2DABL 0x70000 /* L2 Memory Disable. */
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+
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+/* Bit masks for SECURE_CONTROL */
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+
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+#define SECURE0 0x1 /* SECURE 0 */
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+#define SECURE1 0x2 /* SECURE 1 */
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+#define SECURE2 0x4 /* SECURE 2 */
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+#define SECURE3 0x8 /* SECURE 3 */
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+
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+/* Bit masks for SECURE_STATUS */
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+
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+#define SECMODE 0x3 /* Secured Mode Control State */
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+#define NMI 0x4 /* Non Maskable Interrupt */
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+#define AFVALID 0x8 /* Authentication Firmware Valid */
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+#define AFEXIT 0x10 /* Authentication Firmware Exit */
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+#define SECSTAT 0xe0 /* Secure Status */
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+
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+/* SWRST Masks */
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+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
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+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
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+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
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+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
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+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
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+
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+/* Bit masks for EPPIx_STATUS */
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+
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+#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
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+#define YFIFO_ERR 0x2 /* Luma FIFO Error */
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+#define LTERR_OVR 0x4 /* Line Track Overflow */
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+#define LTERR_UNDR 0x8 /* Line Track Underflow */
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+#define FTERR_OVR 0x10 /* Frame Track Overflow */
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+#define FTERR_UNDR 0x20 /* Frame Track Underflow */
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+#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
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+#define DMA1URQ 0x80 /* DMA1 Urgent Request */
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吉超博