|
|
@@ -2225,3 +2225,135 @@ static __initdata struct clk *init_clocks[] = {
|
|
|
&pio1_mck,
|
|
|
&pio2_mck,
|
|
|
&pio3_mck,
|
|
|
+ &pio4_mck,
|
|
|
+ &at32_tcb0_t0_clk,
|
|
|
+ &at32_tcb1_t0_clk,
|
|
|
+ &atmel_psif0_pclk,
|
|
|
+ &atmel_psif1_pclk,
|
|
|
+ &atmel_usart0_usart,
|
|
|
+ &atmel_usart1_usart,
|
|
|
+ &atmel_usart2_usart,
|
|
|
+ &atmel_usart3_usart,
|
|
|
+ &atmel_pwm0_mck,
|
|
|
+#if defined(CONFIG_CPU_AT32AP7000)
|
|
|
+ &macb0_hclk,
|
|
|
+ &macb0_pclk,
|
|
|
+ &macb1_hclk,
|
|
|
+ &macb1_pclk,
|
|
|
+#endif
|
|
|
+ &atmel_spi0_spi_clk,
|
|
|
+ &atmel_spi1_spi_clk,
|
|
|
+ &atmel_twi0_pclk,
|
|
|
+ &atmel_mci0_pclk,
|
|
|
+#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
|
|
|
+ &atmel_lcdfb0_hck1,
|
|
|
+ &atmel_lcdfb0_pixclk,
|
|
|
+#endif
|
|
|
+ &ssc0_pclk,
|
|
|
+ &ssc1_pclk,
|
|
|
+ &ssc2_pclk,
|
|
|
+ &usba0_hclk,
|
|
|
+ &usba0_pclk,
|
|
|
+ &atmel_ac97c0_pclk,
|
|
|
+ &abdac0_pclk,
|
|
|
+ &abdac0_sample_clk,
|
|
|
+ &gclk0,
|
|
|
+ &gclk1,
|
|
|
+ &gclk2,
|
|
|
+ &gclk3,
|
|
|
+ &gclk4,
|
|
|
+};
|
|
|
+
|
|
|
+void __init setup_platform(void)
|
|
|
+{
|
|
|
+ u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
|
|
|
+ main_clock = &pll0;
|
|
|
+ cpu_clk.parent = &pll0;
|
|
|
+ } else {
|
|
|
+ main_clock = &osc0;
|
|
|
+ cpu_clk.parent = &osc0;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (pm_readl(PLL0) & PM_BIT(PLLOSC))
|
|
|
+ pll0.parent = &osc1;
|
|
|
+ if (pm_readl(PLL1) & PM_BIT(PLLOSC))
|
|
|
+ pll1.parent = &osc1;
|
|
|
+
|
|
|
+ genclk_init_parent(&gclk0);
|
|
|
+ genclk_init_parent(&gclk1);
|
|
|
+ genclk_init_parent(&gclk2);
|
|
|
+ genclk_init_parent(&gclk3);
|
|
|
+ genclk_init_parent(&gclk4);
|
|
|
+#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
|
|
|
+ genclk_init_parent(&atmel_lcdfb0_pixclk);
|
|
|
+#endif
|
|
|
+ genclk_init_parent(&abdac0_sample_clk);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Build initial dynamic clock list by registering all clocks
|
|
|
+ * from the array.
|
|
|
+ * At the same time, turn on all clocks that have at least one
|
|
|
+ * user already, and turn off everything else. We only do this
|
|
|
+ * for module clocks, and even though it isn't particularly
|
|
|
+ * pretty to check the address of the mode function, it should
|
|
|
+ * do the trick...
|
|
|
+ */
|
|
|
+ for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
|
|
|
+ struct clk *clk = init_clocks[i];
|
|
|
+
|
|
|
+ /* first, register clock */
|
|
|
+ at32_clk_register(clk);
|
|
|
+
|
|
|
+ if (clk->users == 0)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ if (clk->mode == &cpu_clk_mode)
|
|
|
+ cpu_mask |= 1 << clk->index;
|
|
|
+ else if (clk->mode == &hsb_clk_mode)
|
|
|
+ hsb_mask |= 1 << clk->index;
|
|
|
+ else if (clk->mode == &pba_clk_mode)
|
|
|
+ pba_mask |= 1 << clk->index;
|
|
|
+ else if (clk->mode == &pbb_clk_mode)
|
|
|
+ pbb_mask |= 1 << clk->index;
|
|
|
+ }
|
|
|
+
|
|
|
+ pm_writel(CPU_MASK, cpu_mask);
|
|
|
+ pm_writel(HSB_MASK, hsb_mask);
|
|
|
+ pm_writel(PBA_MASK, pba_mask);
|
|
|
+ pm_writel(PBB_MASK, pbb_mask);
|
|
|
+
|
|
|
+ /* Initialize the port muxes */
|
|
|
+ at32_init_pio(&pio0_device);
|
|
|
+ at32_init_pio(&pio1_device);
|
|
|
+ at32_init_pio(&pio2_device);
|
|
|
+ at32_init_pio(&pio3_device);
|
|
|
+ at32_init_pio(&pio4_device);
|
|
|
+}
|
|
|
+
|
|
|
+struct gen_pool *sram_pool;
|
|
|
+
|
|
|
+static int __init sram_init(void)
|
|
|
+{
|
|
|
+ struct gen_pool *pool;
|
|
|
+
|
|
|
+ /* 1KiB granularity */
|
|
|
+ pool = gen_pool_create(10, -1);
|
|
|
+ if (!pool)
|
|
|
+ goto fail;
|
|
|
+
|
|
|
+ if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
|
|
|
+ goto err_pool_add;
|
|
|
+
|
|
|
+ sram_pool = pool;
|
|
|
+ return 0;
|
|
|
+
|
|
|
+err_pool_add:
|
|
|
+ gen_pool_destroy(pool);
|
|
|
+fail:
|
|
|
+ pr_err("Failed to create SRAM pool\n");
|
|
|
+ return -ENOMEM;
|
|
|
+}
|
|
|
+core_initcall(sram_init);
|
李欣儒