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+/*
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+ * OMAP44xx CM1 instance offset macros
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+ *
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+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
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+ * Copyright (C) 2009-2010 Nokia Corporation
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+ *
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+ * Paul Walmsley (paul@pwsan.com)
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+ * Rajendra Nayak (rnayak@ti.com)
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+ * Benoit Cousson (b-cousson@ti.com)
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+ *
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+ * This file is automatically generated from the OMAP hardware databases.
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+ * We respectfully ask that any modifications to this file be coordinated
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+ * with the public linux-omap@vger.kernel.org mailing list and the
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+ * authors above to ensure that the autogeneration scripts are kept
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+ * up-to-date with the file contents.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
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+ * or "OMAP4430".
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+ */
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+
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+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
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+#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
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+
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+/* CM1 base address */
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+#define OMAP4430_CM1_BASE 0x4a004000
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+
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+#define OMAP44XX_CM1_REGADDR(inst, reg) \
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+ OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
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+
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+/* CM1 instances */
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+#define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
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+#define OMAP4430_CM1_CKGEN_INST 0x0100
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+#define OMAP4430_CM1_MPU_INST 0x0300
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+#define OMAP4430_CM1_TESLA_INST 0x0400
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+#define OMAP4430_CM1_ABE_INST 0x0500
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+#define OMAP4430_CM1_RESTORE_INST 0x0e00
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+#define OMAP4430_CM1_INSTR_INST 0x0f00
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+
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+/* CM1 clockdomain register offsets (from instance start) */
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+#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
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+#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
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+#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
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+
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+/* CM1 */
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+
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+/* CM1.OCP_SOCKET_CM1 register offsets */
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+#define OMAP4_REVISION_CM1_OFFSET 0x0000
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+#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
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+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
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+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
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+
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+/* CM1.CKGEN_CM1 register offsets */
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+#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
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+#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
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+#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
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+#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
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+#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
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+#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
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+#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
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+#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
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+#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
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+#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
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+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
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+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
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+#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
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+#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
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+#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
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+#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
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+#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
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+#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
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+#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
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+#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
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+#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
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+#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
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宁志军