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@@ -224,3 +224,187 @@
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/* Interrupt styles
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*/
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+#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
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+#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
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+#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
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+#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
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+#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
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+
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+/*
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+ * Mask used to clear interrupt styles
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+ */
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+#define IXP4XX_GPIO_STYLE_CLEAR 0x7
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+#define IXP4XX_GPIO_STYLE_SIZE 3
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+
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+/*
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+ * Constants to make it easy to access Timer Control/Status registers
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+ */
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+#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
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+#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
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+#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
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+#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
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+#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
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+#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
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+#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
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+#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
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+#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
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+
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+/*
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+ * Operating System Timer Register Definitions.
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+ */
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+
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+#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
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+
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+#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
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+#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
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+#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
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+#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
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+#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
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+#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
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+#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
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+#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
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+#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
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+
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+/*
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+ * Timer register values and bit definitions
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+ */
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+#define IXP4XX_OST_ENABLE 0x00000001
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+#define IXP4XX_OST_ONE_SHOT 0x00000002
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+/* Low order bits of reload value ignored */
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+#define IXP4XX_OST_RELOAD_MASK 0x00000003
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+#define IXP4XX_OST_DISABLED 0x00000000
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+#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
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+#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
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+#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
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+#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
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+#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
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+
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+#define IXP4XX_WDT_KEY 0x0000482E
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+
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+#define IXP4XX_WDT_RESET_ENABLE 0x00000001
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+#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
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+#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
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+
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+
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+/*
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+ * Constants to make it easy to access PCI Control/Status registers
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+ */
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+#define PCI_NP_AD_OFFSET 0x00
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+#define PCI_NP_CBE_OFFSET 0x04
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+#define PCI_NP_WDATA_OFFSET 0x08
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+#define PCI_NP_RDATA_OFFSET 0x0c
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+#define PCI_CRP_AD_CBE_OFFSET 0x10
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+#define PCI_CRP_WDATA_OFFSET 0x14
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+#define PCI_CRP_RDATA_OFFSET 0x18
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+#define PCI_CSR_OFFSET 0x1c
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+#define PCI_ISR_OFFSET 0x20
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+#define PCI_INTEN_OFFSET 0x24
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+#define PCI_DMACTRL_OFFSET 0x28
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+#define PCI_AHBMEMBASE_OFFSET 0x2c
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+#define PCI_AHBIOBASE_OFFSET 0x30
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+#define PCI_PCIMEMBASE_OFFSET 0x34
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+#define PCI_AHBDOORBELL_OFFSET 0x38
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+#define PCI_PCIDOORBELL_OFFSET 0x3C
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+#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
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+#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
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+#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
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+#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
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+#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
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+#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
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+
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+/*
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+ * PCI Control/Status Registers
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+ */
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+#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
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+
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+#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
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+#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
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+#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
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+#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
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+#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
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+#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
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+#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
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+#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
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+#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
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+#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
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+#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
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+#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
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+#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
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+#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
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+#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
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+#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
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+#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
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+#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
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+#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
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+#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
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+#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
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+#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
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+
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+/*
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+ * PCI register values and bit definitions
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+ */
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+
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+/* CSR bit definitions */
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+#define PCI_CSR_HOST 0x00000001
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+#define PCI_CSR_ARBEN 0x00000002
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+#define PCI_CSR_ADS 0x00000004
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+#define PCI_CSR_PDS 0x00000008
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+#define PCI_CSR_ABE 0x00000010
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+#define PCI_CSR_DBT 0x00000020
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+#define PCI_CSR_ASE 0x00000100
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+#define PCI_CSR_IC 0x00008000
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+
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+/* ISR (Interrupt status) Register bit definitions */
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+#define PCI_ISR_PSE 0x00000001
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+#define PCI_ISR_PFE 0x00000002
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+#define PCI_ISR_PPE 0x00000004
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+#define PCI_ISR_AHBE 0x00000008
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+#define PCI_ISR_APDC 0x00000010
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+#define PCI_ISR_PADC 0x00000020
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+#define PCI_ISR_ADB 0x00000040
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+#define PCI_ISR_PDB 0x00000080
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+
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+/* INTEN (Interrupt Enable) Register bit definitions */
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+#define PCI_INTEN_PSE 0x00000001
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+#define PCI_INTEN_PFE 0x00000002
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+#define PCI_INTEN_PPE 0x00000004
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+#define PCI_INTEN_AHBE 0x00000008
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+#define PCI_INTEN_APDC 0x00000010
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+#define PCI_INTEN_PADC 0x00000020
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+#define PCI_INTEN_ADB 0x00000040
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+#define PCI_INTEN_PDB 0x00000080
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+
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+/*
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+ * Shift value for byte enable on NP cmd/byte enable register
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+ */
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+#define IXP4XX_PCI_NP_CBE_BESL 4
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+
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+/*
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+ * PCI commands supported by NP access unit
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+ */
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+#define NP_CMD_IOREAD 0x2
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+#define NP_CMD_IOWRITE 0x3
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+#define NP_CMD_CONFIGREAD 0xa
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+#define NP_CMD_CONFIGWRITE 0xb
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+#define NP_CMD_MEMREAD 0x6
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+#define NP_CMD_MEMWRITE 0x7
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+
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+/*
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+ * Constants for CRP access into local config space
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+ */
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+#define CRP_AD_CBE_BESL 20
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+#define CRP_AD_CBE_WRITE 0x00010000
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+
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+
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+/*
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+ * USB Device Controller
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+ *
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+ * These are used by the USB gadget driver, so they don't follow the
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+ * IXP4XX_ naming convetions.
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+ *
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+ */
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+# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
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+
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+/* UDC Undocumented - Reserved1 */
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+#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
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+/* UDC Undocumented - Reserved2 */
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