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@@ -952,3 +952,169 @@ static struct platform_device spu0_device = {
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.dev = {
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.platform_data = &spu0_platform_data,
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},
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+ .resource = spu0_resources,
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+ .num_resources = ARRAY_SIZE(spu0_resources),
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+};
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+
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+/* SPU2DSP1 */
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+static struct uio_info spu1_platform_data = {
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+ .name = "SPU2DSP1",
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+ .version = "0",
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+ .irq = evt2irq(0x1820),
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+};
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+
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+static struct resource spu1_resources[] = {
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+ [0] = {
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+ .name = "SPU2DSP1",
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+ .start = 0xfe300000,
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+ .end = 0xfe3fffff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+static struct platform_device spu1_device = {
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+ .name = "uio_pdrv_genirq",
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+ .id = 7,
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+ .dev = {
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+ .platform_data = &spu1_platform_data,
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+ },
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+ .resource = spu1_resources,
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+ .num_resources = ARRAY_SIZE(spu1_resources),
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+};
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+
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+static struct platform_device *sh7372_early_devices[] __initdata = {
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+ &scif0_device,
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+ &scif1_device,
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+ &scif2_device,
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+ &scif3_device,
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+ &scif4_device,
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+ &scif5_device,
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+ &scif6_device,
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+ &cmt2_device,
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+ &tmu00_device,
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+ &tmu01_device,
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+};
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+
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+static struct platform_device *sh7372_late_devices[] __initdata = {
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+ &iic0_device,
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+ &iic1_device,
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+ &dma0_device,
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+ &dma1_device,
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+ &dma2_device,
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+ &usb_dma0_device,
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+ &usb_dma1_device,
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+ &vpu_device,
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+ &veu0_device,
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+ &veu1_device,
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+ &veu2_device,
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+ &veu3_device,
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+ &jpu_device,
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+ &spu0_device,
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+ &spu1_device,
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+};
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+
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+void __init sh7372_add_standard_devices(void)
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+{
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+ struct pm_domain_device domain_devices[] = {
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+ { "A3RV", &vpu_device, },
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+ { "A4MP", &spu0_device, },
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+ { "A4MP", &spu1_device, },
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+ { "A3SP", &scif0_device, },
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+ { "A3SP", &scif1_device, },
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+ { "A3SP", &scif2_device, },
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+ { "A3SP", &scif3_device, },
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+ { "A3SP", &scif4_device, },
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+ { "A3SP", &scif5_device, },
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+ { "A3SP", &scif6_device, },
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+ { "A3SP", &iic1_device, },
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+ { "A3SP", &dma0_device, },
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+ { "A3SP", &dma1_device, },
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+ { "A3SP", &dma2_device, },
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+ { "A3SP", &usb_dma0_device, },
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+ { "A3SP", &usb_dma1_device, },
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+ { "A4R", &iic0_device, },
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+ { "A4R", &veu0_device, },
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+ { "A4R", &veu1_device, },
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+ { "A4R", &veu2_device, },
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+ { "A4R", &veu3_device, },
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+ { "A4R", &jpu_device, },
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+ { "A4R", &tmu00_device, },
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+ { "A4R", &tmu01_device, },
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+ };
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+
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+ sh7372_init_pm_domains();
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+
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+ platform_add_devices(sh7372_early_devices,
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+ ARRAY_SIZE(sh7372_early_devices));
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+
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+ platform_add_devices(sh7372_late_devices,
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+ ARRAY_SIZE(sh7372_late_devices));
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+
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+ rmobile_add_devices_to_domains(domain_devices,
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+ ARRAY_SIZE(domain_devices));
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+}
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+
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+static void __init sh7372_earlytimer_init(void)
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+{
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+ sh7372_clock_init();
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+ shmobile_earlytimer_init();
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+}
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+
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+void __init sh7372_add_early_devices(void)
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+{
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+ early_platform_add_devices(sh7372_early_devices,
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+ ARRAY_SIZE(sh7372_early_devices));
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+
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+ /* setup early console here as well */
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+ shmobile_setup_console();
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+
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+ /* override timer setup with soc-specific code */
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+ shmobile_timer.init = sh7372_earlytimer_init;
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+}
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+
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+#ifdef CONFIG_USE_OF
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+
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+void __init sh7372_add_early_devices_dt(void)
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+{
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+ shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
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+
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+ early_platform_add_devices(sh7372_early_devices,
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+ ARRAY_SIZE(sh7372_early_devices));
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+
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+ /* setup early console here as well */
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+ shmobile_setup_console();
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+}
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+
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+static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
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+ { }
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+};
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+
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+void __init sh7372_add_standard_devices_dt(void)
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+{
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+ /* clocks are setup late during boot in the case of DT */
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+ sh7372_clock_init();
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+
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+ platform_add_devices(sh7372_early_devices,
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+ ARRAY_SIZE(sh7372_early_devices));
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+
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+ of_platform_populate(NULL, of_default_bus_match_table,
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+ sh7372_auxdata_lookup, NULL);
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+}
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+
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+static const char *sh7372_boards_compat_dt[] __initdata = {
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+ "renesas,sh7372",
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+ NULL,
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+};
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+
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+DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
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+ .map_io = sh7372_map_io,
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+ .init_early = sh7372_add_early_devices_dt,
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+ .nr_irqs = NR_IRQS_LEGACY,
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+ .init_irq = sh7372_init_irq,
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+ .handle_irq = shmobile_handle_irq_intc,
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+ .init_machine = sh7372_add_standard_devices_dt,
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+ .timer = &shmobile_timer,
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+ .dt_compat = sh7372_boards_compat_dt,
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+MACHINE_END
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+
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+#endif /* CONFIG_USE_OF */
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