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@@ -0,0 +1,93 @@
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+//----------------------------------------------------------------------------
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+//
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+// File generated by S1D13806CFG.EXE
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+//
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+// Copyright (c) 2000,2001 Epson Research and Development, Inc.
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+// All rights reserved.
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+//
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+//----------------------------------------------------------------------------
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+
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+// Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
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+// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
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+
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+#define SWIVEL_VIEW 0 /* 0:none, 1:90 not completed */
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+
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+static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
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+
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+ {0x0001,0x00}, // Miscellaneous Register
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+ {0x01FC,0x00}, // Display Mode Register
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+#if defined(CONFIG_PLAT_MAPPI)
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+ {0x0004,0x00}, // General IO Pins Configuration Register 0
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+ {0x0005,0x00}, // General IO Pins Configuration Register 1
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+ {0x0008,0x00}, // General IO Pins Control Register 0
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+ {0x0009,0x00}, // General IO Pins Control Register 1
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+ {0x0010,0x00}, // Memory Clock Configuration Register
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+ {0x0014,0x00}, // LCD Pixel Clock Configuration Register
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+ {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
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+ {0x001C,0x00}, // MediaPlug Clock Configuration Register
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+/*
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+ * .. 10MHz: 0x00
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+ * .. 30MHz: 0x01
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+ * 30MHz ..: 0x02
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+ */
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+ {0x001E,0x02}, // CPU To Memory Wait State Select Register
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+ {0x0021,0x02}, // DRAM Refresh Rate Register
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+ {0x002A,0x11}, // DRAM Timings Control Register 0
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+ {0x002B,0x13}, // DRAM Timings Control Register 1
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+ {0x0020,0x80}, // Memory Configuration Register
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+ {0x0030,0x25}, // Panel Type Register
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+ {0x0031,0x00}, // MOD Rate Register
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+ {0x0032,0x4F}, // LCD Horizontal Display Width Register
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+ {0x0034,0x12}, // LCD Horizontal Non-Display Period Register
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+ {0x0035,0x01}, // TFT FPLINE Start Position Register
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+ {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
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+ {0x0038,0xDF}, // LCD Vertical Display Height Register 0
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+ {0x0039,0x01}, // LCD Vertical Display Height Register 1
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+ {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
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+ {0x003B,0x0A}, // TFT FPFRAME Start Position Register
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+ {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
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+
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+ {0x0041,0x00}, // LCD Miscellaneous Register
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+ {0x0042,0x00}, // LCD Display Start Address Register 0
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+ {0x0043,0x00}, // LCD Display Start Address Register 1
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+ {0x0044,0x00}, // LCD Display Start Address Register 2
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+
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+#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
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+ {0x0004,0x07}, // GPIO[0:7] direction
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+ {0x0005,0x00}, // GPIO[8:12] direction
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+ {0x0008,0x00}, // GPIO[0:7] data
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+ {0x0009,0x00}, // GPIO[8:12] data
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+ {0x0008,0x04}, // LCD panel Vcc on
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+ {0x0008,0x05}, // LCD panel reset
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+ {0x0010,0x01}, // Memory Clock Configuration Register
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+ {0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
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+ {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
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+ {0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz)
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+ {0x001E,0x00}, // CPU To Memory Wait State Select Register
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+ {0x0020,0x80}, // Memory Configuration Register
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+ {0x0021,0x03}, // DRAM Refresh Rate Register
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+ {0x002A,0x00}, // DRAM Timings Control Register 0
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+ {0x002B,0x01}, // DRAM Timings Control Register 1
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+ {0x0030,0x25}, // Panel Type Register
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+ {0x0031,0x00}, // MOD Rate Register
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+ {0x0032,0x1d}, // LCD Horizontal Display Width Register
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+ {0x0034,0x05}, // LCD Horizontal Non-Display Period Register
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+ {0x0035,0x01}, // TFT FPLINE Start Position Register
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+ {0x0036,0x01}, // TFT FPLINE Pulse Width Register
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+ {0x0038,0x3F}, // LCD Vertical Display Height Register 0
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+ {0x0039,0x01}, // LCD Vertical Display Height Register 1
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+ {0x003A,0x0b}, // LCD Vertical Non-Display Period Register
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+ {0x003B,0x07}, // TFT FPFRAME Start Position Register
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+ {0x003C,0x02}, // TFT FPFRAME Pulse Width Register
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+
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+ {0x0041,0x00}, // LCD Miscellaneous Register
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+#if (SWIVEL_VIEW == 0)
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+ {0x0042,0x00}, // LCD Display Start Address Register 0
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+ {0x0043,0x00}, // LCD Display Start Address Register 1
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+ {0x0044,0x00}, // LCD Display Start Address Register 2
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+
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+#elif (SWIVEL_VIEW == 1)
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+ // 1024 - W(320) = 0x2C0
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+ {0x0042,0xC0}, // LCD Display Start Address Register 0
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+ {0x0043,0x02}, // LCD Display Start Address Register 1
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+ {0x0044,0x00}, // LCD Display Start Address Register 2
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