efHotAgingTrendMining memoryCall.h 李欣儒 commit at 2020-12-24

efHotAgingTrendMining/dataSharedMemory/memoryCall.h

@@ -875,3 +875,125 @@
  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
  * CM_CLKSEL_DPLL_UNIPRO
  */
+#define OMAP4430_DPLL_MULT_SHIFT				8
+#define OMAP4430_DPLL_MULT_WIDTH				0xb
+#define OMAP4430_DPLL_MULT_MASK					(0x7ff << 8)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_MULT_USB_SHIFT				8
+#define OMAP4430_DPLL_MULT_USB_WIDTH				0xc
+#define OMAP4430_DPLL_MULT_USB_MASK				(0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO
+ */
+#define OMAP4430_DPLL_REGM4XEN_SHIFT				11
+#define OMAP4430_DPLL_REGM4XEN_WIDTH				0x1
+#define OMAP4430_DPLL_REGM4XEN_MASK				(1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_SD_DIV_SHIFT				24
+#define OMAP4430_DPLL_SD_DIV_WIDTH				0x8
+#define OMAP4430_DPLL_SD_DIV_MASK				(0xff << 24)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP4430_DPLL_SSC_ACK_SHIFT				13
+#define OMAP4430_DPLL_SSC_ACK_WIDTH				0x1
+#define OMAP4430_DPLL_SSC_ACK_MASK				(1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT			14
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH			0x1
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK			(1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP4430_DPLL_SSC_EN_SHIFT				12
+#define OMAP4430_DPLL_SSC_EN_WIDTH				0x1
+#define OMAP4430_DPLL_SSC_EN_MASK				(1 << 12)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP4430_DSS_DYNDEP_SHIFT				8
+#define OMAP4430_DSS_DYNDEP_WIDTH				0x1
+#define OMAP4430_DSS_DYNDEP_MASK				(1 << 8)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
+#define OMAP4430_DSS_STATDEP_SHIFT				8
+#define OMAP4430_DSS_STATDEP_WIDTH				0x1
+#define OMAP4430_DSS_STATDEP_MASK				(1 << 8)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_DUCATI_DYNDEP_SHIFT				0
+#define OMAP4430_DUCATI_DYNDEP_WIDTH				0x1
+#define OMAP4430_DUCATI_DYNDEP_MASK				(1 << 0)
+
+/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
+#define OMAP4430_DUCATI_STATDEP_SHIFT				0
+#define OMAP4430_DUCATI_STATDEP_WIDTH				0x1
+#define OMAP4430_DUCATI_STATDEP_MASK				(1 << 0)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_FREQ_UPDATE_SHIFT				0
+#define OMAP4430_FREQ_UPDATE_WIDTH				0x1
+#define OMAP4430_FREQ_UPDATE_MASK				(1 << 0)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_FUNC_SHIFT					16
+#define OMAP4430_FUNC_WIDTH					0xc
+#define OMAP4430_FUNC_MASK					(0xfff << 16)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_GFX_DYNDEP_SHIFT				10
+#define OMAP4430_GFX_DYNDEP_WIDTH				0x1
+#define OMAP4430_GFX_DYNDEP_MASK				(1 << 10)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP4430_GFX_STATDEP_SHIFT				10
+#define OMAP4430_GFX_STATDEP_WIDTH				0x1
+#define OMAP4430_GFX_STATDEP_MASK				(1 << 10)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT				0
+#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH				0x1
+#define OMAP4430_GPMC_FREQ_UPDATE_MASK				(1 << 0)
+
+/*
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT			0
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH			0x5
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK			(0x1f << 0)
+
+/*
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT		5
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH		0x1
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK		(1 << 5)
+
+/*
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT		8
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH		0x1
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK		(1 << 8)
+
+/*
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER