|
|
@@ -0,0 +1,93 @@
|
|
|
+/*
|
|
|
+ * Copyright 2008-2010 Analog Devices Inc.
|
|
|
+ *
|
|
|
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
|
|
|
+ */
|
|
|
+
|
|
|
+#ifndef _CDEF_BF512_H
|
|
|
+#define _CDEF_BF512_H
|
|
|
+
|
|
|
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
|
|
|
+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
|
|
|
+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
|
|
|
+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
|
|
|
+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
|
|
|
+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
|
|
|
+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
|
|
|
+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
|
|
|
+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
|
|
|
+#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
|
|
+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
|
|
+
|
|
|
+
|
|
|
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
|
|
|
+#define bfin_read_SWRST() bfin_read16(SWRST)
|
|
|
+#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
|
|
+#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
|
|
+#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
|
|
+
|
|
|
+#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
|
|
|
+#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
|
|
|
+#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
|
|
|
+#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
|
|
|
+#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
|
|
|
+#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
|
|
|
+
|
|
|
+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
|
|
|
+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
|
|
|
+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
|
|
|
+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
|
|
|
+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
|
|
|
+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
|
|
|
+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
|
|
|
+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
|
|
|
+
|
|
|
+#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
|
|
|
+#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
|
|
|
+#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
|
|
|
+#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
|
|
|
+
|
|
|
+#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
|
|
|
+#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
|
|
|
+#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
|
|
|
+#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
|
|
|
+
|
|
|
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
|
|
|
+
|
|
|
+#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
|
|
|
+#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
|
|
|
+#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
|
|
|
+#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
|
|
|
+#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
|
|
|
+#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
|
|
|
+#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
|
|
|
+#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
|
|
|
+#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
|
|
|
+#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
|
|
|
+#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
|
|
|
+#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
|
|
|
+#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
|
|
|
+#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
|
|
|
+
|
|
|
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
|
|
|
+#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
|
|
|
+#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
|
|
|
+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
|
|
|
+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
|
|
|
+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
|
|
|
+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
|
|
|
+
|
|
|
+
|
|
|
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
|
|
|
+#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
|
|
|
+#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
|
|
|
+#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
|
|
|
+#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
|
|
|
+#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
|
|
|
+#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
|
|
|
+#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
|
|
|
+#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
|
|
|
+#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
|
|
|
+#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
|
|
|
+#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
|
|
|
+#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
|
韩正义