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@@ -241,3 +241,124 @@
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/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
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#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
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+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7)
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+
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+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
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+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7
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+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7)
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+
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+/* Used by PM_DSS_PWRSTCTRL */
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+#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16
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+#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16)
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+
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+/* Used by PM_DSS_PWRSTCTRL */
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+#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8
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+#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8)
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+
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+/* Used by PM_DSS_PWRSTST */
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+#define OMAP4430_DSS_MEM_STATEST_SHIFT 4
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+#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20
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+#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10
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+#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10)
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+
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+/* Used by PM_CORE_PWRSTST */
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+#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8
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+#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22
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+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11
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+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11)
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+
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+/* Used by PM_CORE_PWRSTST */
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+#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
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+#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
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+
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+/* Used by PRM_DEVICE_OFF_CTRL */
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+#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8
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+#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
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+
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+/* Used by PRM_DEVICE_OFF_CTRL */
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+#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9
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+#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
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+
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+/* Used by RM_MPU_RSTST */
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+#define OMAP4430_EMULATION_RST_SHIFT 0
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+#define OMAP4430_EMULATION_RST_MASK (1 << 0)
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+
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+/* Used by RM_DUCATI_RSTST */
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+#define OMAP4430_EMULATION_RST1ST_SHIFT 3
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+#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3)
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+
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+/* Used by RM_DUCATI_RSTST */
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+#define OMAP4430_EMULATION_RST2ST_SHIFT 4
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+#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4)
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+
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+/* Used by RM_IVAHD_RSTST */
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+#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3
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+#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3)
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+
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+/* Used by RM_IVAHD_RSTST */
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+#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4
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+#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4)
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+
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+/* Used by PM_EMU_PWRSTCTRL */
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+#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16
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+#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16)
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+
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+/* Used by PM_EMU_PWRSTST */
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+#define OMAP4430_EMU_BANK_STATEST_SHIFT 4
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+#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4)
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+
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+/*
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+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
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+ * PRM_LDO_SRAM_MPU_SETUP
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+ */
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+#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3
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+#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3)
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+
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+/*
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+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
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+ * PRM_LDO_SRAM_MPU_SETUP
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+ */
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+#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5
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+#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5)
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+
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+/*
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+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
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+ * PRM_LDO_SRAM_MPU_SETUP
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+ */
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+#define OMAP4430_ENFUNC4_SHIFT 6
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+#define OMAP4430_ENFUNC4_MASK (1 << 6)
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+
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+/*
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+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
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+ * PRM_LDO_SRAM_MPU_SETUP
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+ */
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+#define OMAP4430_ENFUNC5_SHIFT 7
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+#define OMAP4430_ENFUNC5_MASK (1 << 7)
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+
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+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
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+#define OMAP4430_ERRORGAIN_SHIFT 16
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+#define OMAP4430_ERRORGAIN_MASK (0xff << 16)
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+
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+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
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+#define OMAP4430_ERROROFFSET_SHIFT 24
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+#define OMAP4430_ERROROFFSET_MASK (0xff << 24)
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+
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+/* Used by PRM_RSTST */
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+#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
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+#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5)
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+
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+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
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+#define OMAP4430_FORCEUPDATE_SHIFT 1
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+#define OMAP4430_FORCEUPDATE_MASK (1 << 1)
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