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+/*
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+ * OMAP44xx Clock Management register bits
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+ *
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+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
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+ * Copyright (C) 2009-2010 Nokia Corporation
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+ *
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+ * Paul Walmsley (paul@pwsan.com)
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+ * Rajendra Nayak (rnayak@ti.com)
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+ * Benoit Cousson (b-cousson@ti.com)
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+ *
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+ * This file is automatically generated from the OMAP hardware databases.
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+ * We respectfully ask that any modifications to this file be coordinated
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+ * with the public linux-omap@vger.kernel.org mailing list and the
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+ * authors above to ensure that the autogeneration scripts are kept
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+ * up-to-date with the file contents.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
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+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
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+
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+/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
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+#define OMAP4430_ABE_DYNDEP_SHIFT 3
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+#define OMAP4430_ABE_DYNDEP_WIDTH 0x1
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+#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
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+
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+/*
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+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
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+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
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+ */
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+#define OMAP4430_ABE_STATDEP_SHIFT 3
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+#define OMAP4430_ABE_STATDEP_WIDTH 0x1
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+#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
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+
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+/* Used by CM_L4CFG_DYNAMICDEP */
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+#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
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+#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1
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+#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
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+
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+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
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+#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16
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+#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1
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+#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16)
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+
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+/*
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+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
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+ * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
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+ * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
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+ */
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+#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
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+#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3
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+#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
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+
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+/* Used by CM_L4CFG_DYNAMICDEP */
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+#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
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+#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1
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+#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
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+
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+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
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+#define OMAP4430_CEFUSE_STATDEP_SHIFT 17
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+#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1
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+#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17)
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+
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+/* Used by CM1_ABE_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
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+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
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+
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+/* Used by CM1_ABE_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12
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+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12)
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+
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+/* Used by CM_WKUP_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
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+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
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+
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+/* Used by CM1_ABE_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11
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+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11)
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+
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+/* Used by CM1_ABE_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
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+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
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+
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+/* Used by CM_MEMIF_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
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+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
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+
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+/* Used by CM_MEMIF_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
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+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
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+
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+/* Used by CM_MEMIF_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
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+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
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+
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+/* Used by CM_CAM_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9
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+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9)
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+
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+/* Used by CM_ALWON_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12
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+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12)
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+
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+/* Used by CM_EMU_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
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+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
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+
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+/* Used by CM_L4CFG_CLKSTCTRL */
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+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
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+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1
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+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
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+
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+/* Used by CM_CEFUSE_CLKSTCTRL */
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+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
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+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1
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+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
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