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@@ -1657,3 +1657,93 @@
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#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
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#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
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#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
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#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
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#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
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#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
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+#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
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+#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
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+#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
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+#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
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+#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
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+#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
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+#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
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+#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
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+#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
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+#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
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+#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
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+#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
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+#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
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+#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
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+#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
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+
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+/* ********************** SDRAM CONTROLLER MASKS *************************** */
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+/* EBIU_SDGCTL Masks */
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+#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
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+#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
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+#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
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+#define PFE 0x00000010 /* Enable SDRAM prefetch */
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+#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
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+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
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+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
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+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
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+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
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+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
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+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
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+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
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+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
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+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
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+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
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+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
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+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
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+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
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+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
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+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
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+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
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+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
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+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
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+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
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+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
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+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
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+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
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+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
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+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
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+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
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+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
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+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
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+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
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+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
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+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
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+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
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+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
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+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
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+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
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+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
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+#define PUPSD 0x00200000 /*Power-up start delay */
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+#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
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+#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
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+#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
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+#define EBUFE 0x02000000 /* Enable external buffering timing */
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+#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
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+#define EMREN 0x10000000 /* Extended mode register enable */
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+#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
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+#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
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+
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+/* EBIU_SDBCTL Masks */
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+#define EBE 0x00000001 /* Enable SDRAM external bank */
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+#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
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+#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
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+#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
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+#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
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+#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */
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+#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */
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+#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
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+#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
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+#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
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+#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
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+
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+/* EBIU_SDSTAT Masks */
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+#define SDCI 0x00000001 /* SDRAM controller is idle */
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+#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
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+#define SDPUA 0x00000004 /* SDRAM power up active */
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+#define SDRS 0x00000008 /* SDRAM is in reset state */
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+#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
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+#define BGSTAT 0x00000020 /* Bus granted */
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+
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+#endif
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