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@@ -325,3 +325,94 @@ apecs_init_arch(void)
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{
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struct pci_controller *hose;
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+ /*
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+ * Create our single hose.
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+ */
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+
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+ pci_isa_hose = hose = alloc_pci_controller();
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+ hose->io_space = &ioport_resource;
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+ hose->mem_space = &iomem_resource;
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+ hose->index = 0;
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+
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+ hose->sparse_mem_base = APECS_SPARSE_MEM - IDENT_ADDR;
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+ hose->dense_mem_base = APECS_DENSE_MEM - IDENT_ADDR;
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+ hose->sparse_io_base = APECS_IO - IDENT_ADDR;
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+ hose->dense_io_base = 0;
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+
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+ /*
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+ * Set up the PCI to main memory translation windows.
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+ *
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+ * Window 1 is direct access 1GB at 1GB
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+ * Window 2 is scatter-gather 8MB at 8MB (for isa)
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+ */
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+ hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
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+ hose->sg_pci = NULL;
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+ __direct_map_base = 0x40000000;
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+ __direct_map_size = 0x40000000;
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+
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+ *(vuip)APECS_IOC_PB1R = __direct_map_base | 0x00080000;
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+ *(vuip)APECS_IOC_PM1R = (__direct_map_size - 1) & 0xfff00000U;
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+ *(vuip)APECS_IOC_TB1R = 0;
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+
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+ *(vuip)APECS_IOC_PB2R = hose->sg_isa->dma_base | 0x000c0000;
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+ *(vuip)APECS_IOC_PM2R = (hose->sg_isa->size - 1) & 0xfff00000;
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+ *(vuip)APECS_IOC_TB2R = virt_to_phys(hose->sg_isa->ptes) >> 1;
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+
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+ apecs_pci_tbi(hose, 0, -1);
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+
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+ /*
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+ * Finally, clear the HAXR2 register, which gets used
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+ * for PCI Config Space accesses. That is the way
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+ * we want to use it, and we do not want to depend on
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+ * what ARC or SRM might have left behind...
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+ */
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+ *(vuip)APECS_IOC_HAXR2 = 0;
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+ mb();
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+}
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+
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+void
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+apecs_pci_clr_err(void)
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+{
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+ unsigned int jd;
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+
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+ jd = *(vuip)APECS_IOC_DCSR;
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+ if (jd & 0xffe0L) {
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+ *(vuip)APECS_IOC_SEAR;
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+ *(vuip)APECS_IOC_DCSR = jd | 0xffe1L;
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+ mb();
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+ *(vuip)APECS_IOC_DCSR;
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+ }
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+ *(vuip)APECS_IOC_TBIA = (unsigned int)APECS_IOC_TBIA;
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+ mb();
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+ *(vuip)APECS_IOC_TBIA;
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+}
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+
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+void
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+apecs_machine_check(unsigned long vector, unsigned long la_ptr)
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+{
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+ struct el_common *mchk_header;
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+ struct el_apecs_procdata *mchk_procdata;
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+ struct el_apecs_sysdata_mcheck *mchk_sysdata;
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+
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+ mchk_header = (struct el_common *)la_ptr;
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+
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+ mchk_procdata = (struct el_apecs_procdata *)
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+ (la_ptr + mchk_header->proc_offset
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+ - sizeof(mchk_procdata->paltemp));
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+
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+ mchk_sysdata = (struct el_apecs_sysdata_mcheck *)
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+ (la_ptr + mchk_header->sys_offset);
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+
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+
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+ /* Clear the error before any reporting. */
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+ mb();
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+ mb(); /* magic */
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+ draina();
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+ apecs_pci_clr_err();
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+ wrmces(0x7); /* reset machine check pending flag */
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+ mb();
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+
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+ process_mcheck_info(vector, la_ptr, "APECS",
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+ (mcheck_expected(0)
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+ && (mchk_sysdata->epic_dcsr & 0x0c00UL)));
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+}
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