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@@ -492,3 +492,162 @@ static u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
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}
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}
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/* external transceiver */
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/* external transceiver */
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+ if (cpu_is_omap15xx()) {
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+ omap_cfg_reg(USB2_TXD);
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+ omap_cfg_reg(USB2_TXEN);
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+ omap_cfg_reg(USB2_SEO);
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+ if (nwires != 3)
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+ omap_cfg_reg(USB2_RCV);
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+ /* there is no USB2_SPEED */
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+ } else if (cpu_is_omap16xx()) {
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+ omap_cfg_reg(V6_USB2_TXD);
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+ omap_cfg_reg(W9_USB2_TXEN);
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+ omap_cfg_reg(W5_USB2_SE0);
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+ if (nwires != 3)
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+ omap_cfg_reg(Y5_USB2_RCV);
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+ // FIXME omap_cfg_reg(USB2_SPEED);
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+ } else {
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+ pr_debug("usb%d cpu unrecognized\n", 1);
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+ return 0;
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+ }
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+
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+ // omap_cfg_reg(USB2_SUSP);
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+
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+ switch (nwires) {
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+ case 2:
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+ goto bad;
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+ case 3:
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+ syscon1 = 2;
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+ break;
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+ case 4:
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+ syscon1 = 1;
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+ break;
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+ case 5:
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+ goto bad;
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+ case 6:
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+ syscon1 = 3;
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+ if (cpu_is_omap15xx()) {
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+ omap_cfg_reg(USB2_VP);
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+ omap_cfg_reg(USB2_VM);
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+ } else {
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+ u32 l;
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+
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+ omap_cfg_reg(AA9_USB2_VP);
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+ omap_cfg_reg(R9_USB2_VM);
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+ l = omap_readl(USB_TRANSCEIVER_CTRL);
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+ l |= CONF_USB2_UNI_R;
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+ omap_writel(l, USB_TRANSCEIVER_CTRL);
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+ }
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+ break;
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+ default:
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+bad:
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+ printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
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+ 2, nwires);
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+ }
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+
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+ return syscon1 << 24;
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+}
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+
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+#ifdef CONFIG_ARCH_OMAP15XX
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+
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+/* ULPD_DPLL_CTRL */
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+#define DPLL_IOB (1 << 13)
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+#define DPLL_PLL_ENABLE (1 << 4)
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+#define DPLL_LOCK (1 << 0)
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+
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+/* ULPD_APLL_CTRL */
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+#define APLL_NDPLL_SWITCH (1 << 0)
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+
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+static void __init omap_1510_usb_init(struct omap_usb_config *config)
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+{
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+ unsigned int val;
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+ u16 w;
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+
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+ config->usb0_init(config->pins[0], is_usb0_device(config));
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+ config->usb1_init(config->pins[1]);
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+ config->usb2_init(config->pins[2], 0);
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+
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+ val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
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+ val |= (config->hmc_mode << 1);
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+ omap_writel(val, MOD_CONF_CTRL_0);
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+
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+ printk("USB: hmc %d", config->hmc_mode);
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+ if (config->pins[0])
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+ printk(", usb0 %d wires%s", config->pins[0],
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+ is_usb0_device(config) ? " (dev)" : "");
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+ if (config->pins[1])
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+ printk(", usb1 %d wires", config->pins[1]);
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+ if (config->pins[2])
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+ printk(", usb2 %d wires", config->pins[2]);
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+ printk("\n");
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+
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+ /* use DPLL for 48 MHz function clock */
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+ pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
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+ omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
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+
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+ w = omap_readw(ULPD_APLL_CTRL);
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+ w &= ~APLL_NDPLL_SWITCH;
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+ omap_writew(w, ULPD_APLL_CTRL);
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+
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+ w = omap_readw(ULPD_DPLL_CTRL);
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+ w |= DPLL_IOB | DPLL_PLL_ENABLE;
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+ omap_writew(w, ULPD_DPLL_CTRL);
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+
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+ w = omap_readw(ULPD_SOFT_REQ);
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+ w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
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+ omap_writew(w, ULPD_SOFT_REQ);
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+
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+ while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
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+ cpu_relax();
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+
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+#ifdef CONFIG_USB_GADGET_OMAP
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+ if (config->register_dev) {
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+ int status;
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+
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+ udc_device.dev.platform_data = config;
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+ status = platform_device_register(&udc_device);
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+ if (status)
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+ pr_debug("can't register UDC device, %d\n", status);
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+ /* udc driver gates 48MHz by D+ pullup */
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+ }
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+#endif
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+
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+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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+ if (config->register_host) {
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+ int status;
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+
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+ ohci_device.dev.platform_data = config;
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+ status = platform_device_register(&ohci_device);
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+ if (status)
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+ pr_debug("can't register OHCI device, %d\n", status);
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+ /* hcd explicitly gates 48MHz */
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+ }
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+#endif
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+}
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+
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+#else
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+static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
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+#endif
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+
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+void __init omap1_usb_init(struct omap_usb_config *_pdata)
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+{
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+ struct omap_usb_config *pdata;
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+
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+ pdata = kmemdup(_pdata, sizeof(*pdata), GFP_KERNEL);
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+ if (!pdata)
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+ return;
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+
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+ pdata->usb0_init = omap1_usb0_init;
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+ pdata->usb1_init = omap1_usb1_init;
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+ pdata->usb2_init = omap1_usb2_init;
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+ udc_device_init(pdata);
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+ ohci_device_init(pdata);
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+ otg_device_init(pdata);
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+
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+ if (cpu_is_omap7xx() || cpu_is_omap16xx())
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+ omap_otg_init(pdata);
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+ else if (cpu_is_omap15xx())
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+ omap_1510_usb_init(pdata);
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+ else
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+ printk(KERN_ERR "USB: No init for your chip yet\n");
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+}
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