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@@ -1854,3 +1854,99 @@ static struct omap_clk omap2420_clks[] = {
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CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
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CLK(NULL, "cam_fck", &cam_fck, CK_242X),
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CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
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+ CLK(NULL, "cam_ick", &cam_ick, CK_242X),
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+ CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
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+ CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
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+ CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
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+ CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
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+ CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
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+ CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
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+ CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
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+ CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
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+ CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
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+ CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
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+ CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
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+ CLK(NULL, "fac_ick", &fac_ick, CK_242X),
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+ CLK(NULL, "fac_fck", &fac_fck, CK_242X),
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+ CLK(NULL, "eac_ick", &eac_ick, CK_242X),
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+ CLK(NULL, "eac_fck", &eac_fck, CK_242X),
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+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
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+ CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
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+ CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
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+ CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
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+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
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+ CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
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+ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
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+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
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+ CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
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+ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
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+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
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+ CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
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+ CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
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+ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
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+ CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
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+ CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
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+ CLK(NULL, "des_ick", &des_ick, CK_242X),
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+ CLK("omap-sham", "ick", &sha_ick, CK_242X),
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+ CLK(NULL, "sha_ick", &sha_ick, CK_242X),
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+ CLK("omap_rng", "ick", &rng_ick, CK_242X),
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+ CLK(NULL, "rng_ick", &rng_ick, CK_242X),
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+ CLK("omap-aes", "ick", &aes_ick, CK_242X),
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+ CLK(NULL, "aes_ick", &aes_ick, CK_242X),
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+ CLK(NULL, "pka_ick", &pka_ick, CK_242X),
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+ CLK(NULL, "usb_fck", &usb_fck, CK_242X),
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+ CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
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+ CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
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+ CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
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+ CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
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+ CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
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+};
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+
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+
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+static const char *enable_init_clks[] = {
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+ "apll96_ck",
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+ "apll54_ck",
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+ "sync_32k_ick",
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+ "omapctrl_ick",
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+ "gpmc_fck",
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+ "sdrc_ick",
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+};
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+
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+/*
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+ * init code
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+ */
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+
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+int __init omap2420_clk_init(void)
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+{
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+ struct omap_clk *c;
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+
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+ prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
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+ cpu_mask = RATE_IN_242X;
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+ rate_table = omap2420_rate_table;
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+
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+ omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
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+
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+ omap2xxx_clkt_vps_check_bootloader_rates();
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+
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+ for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
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+ c++) {
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+ clkdev_add(&c->lk);
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+ if (!__clk_init(NULL, c->lk.clk))
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+ omap2_init_clk_hw_omap_clocks(c->lk.clk);
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+ }
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+
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+ omap2xxx_clkt_vps_late_init();
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+
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+ omap2_clk_disable_autoidle_all();
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+
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+ omap2_clk_enable_init_clocks(enable_init_clks,
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+ ARRAY_SIZE(enable_init_clks));
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+
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+ pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
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+ (clk_get_rate(&sys_ck) / 1000000),
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+ (clk_get_rate(&sys_ck) / 100000) % 10,
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+ (clk_get_rate(&dpll_ck) / 1000000),
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+ (clk_get_rate(&mpu_ck) / 1000000));
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+
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+ return 0;
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+}
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