waterDataStatistics memoryCall.h 袁明明 commit at 2021-01-05

waterDataStatistics/dataSharedMemory/memoryCall.h

@@ -1356,3 +1356,81 @@
 #define bfin_write_DMA29_BWM_COUNT(val)		bfin_write32(DMA29_BWM_COUNT, val)
 #define bfin_read_DMA29_CURR_BWM_COUNT()	bfin_read32(DMA29_CURR_BWM_COUNT)
 #define bfin_write_DMA29_CURR_BWM_COUNT(val)	bfin_write32(DMA29_CURR_BWM_COUNT, val)
+
+/* DMA Channel 30 Registers */
+
+#define bfin_read_DMA30_NEXT_DESC_PTR() 	bfin_read32(DMA30_NEXT_DESC_PTR)
+#define bfin_write_DMA30_NEXT_DESC_PTR(val) 	bfin_write32(DMA30_NEXT_DESC_PTR, val)
+#define bfin_read_DMA30_START_ADDR() 		bfin_read32(DMA30_START_ADDR)
+#define bfin_write_DMA30_START_ADDR(val) 	bfin_write32(DMA30_START_ADDR, val)
+#define bfin_read_DMA30_CONFIG()		bfin_read32(DMA30_CONFIG)
+#define bfin_write_DMA30_CONFIG(val)		bfin_write32(DMA30_CONFIG, val)
+#define bfin_read_DMA30_X_COUNT()		bfin_read32(DMA30_X_COUNT)
+#define bfin_write_DMA30_X_COUNT(val)		bfin_write32(DMA30_X_COUNT, val)
+#define bfin_read_DMA30_X_MODIFY()		bfin_read32(DMA30_X_MODIFY)
+#define bfin_write_DMA30_X_MODIFY(val) 		bfin_write32(DMA30_X_MODIFY, val)
+#define bfin_read_DMA30_Y_COUNT()		bfin_read32(DMA30_Y_COUNT)
+#define bfin_write_DMA30_Y_COUNT(val)		bfin_write32(DMA30_Y_COUNT, val)
+#define bfin_read_DMA30_Y_MODIFY()		bfin_read32(DMA30_Y_MODIFY)
+#define bfin_write_DMA30_Y_MODIFY(val) 		bfin_write32(DMA30_Y_MODIFY, val)
+#define bfin_read_DMA30_CURR_DESC_PTR() 	bfin_read32(DMA30_CURR_DESC_PTR)
+#define bfin_write_DMA30_CURR_DESC_PTR(val) 	bfin_write32(DMA30_CURR_DESC_PTR, val)
+#define bfin_read_DMA30_PREV_DESC_PTR() 	bfin_read32(DMA30_PREV_DESC_PTR)
+#define bfin_write_DMA30_PREV_DESC_PTR(val) 	bfin_write32(DMA30_PREV_DESC_PTR, val)
+#define bfin_read_DMA30_CURR_ADDR() 		bfin_read32(DMA30_CURR_ADDR)
+#define bfin_write_DMA30_CURR_ADDR(val) 	bfin_write32(DMA30_CURR_ADDR, val)
+#define bfin_read_DMA30_IRQ_STATUS()		bfin_read32(DMA30_IRQ_STATUS)
+#define bfin_write_DMA30_IRQ_STATUS(val)	bfin_write32(DMA30_IRQ_STATUS, val)
+#define bfin_read_DMA30_CURR_X_COUNT()		bfin_read32(DMA30_CURR_X_COUNT)
+#define bfin_write_DMA30_CURR_X_COUNT(val)	bfin_write32(DMA30_CURR_X_COUNT, val)
+#define bfin_read_DMA30_CURR_Y_COUNT()		bfin_read32(DMA30_CURR_Y_COUNT)
+#define bfin_write_DMA30_CURR_Y_COUNT(val)	bfin_write32(DMA30_CURR_Y_COUNT, val)
+#define bfin_read_DMA30_BWL_COUNT()		bfin_read32(DMA30_BWL_COUNT)
+#define bfin_write_DMA30_BWL_COUNT(val)		bfin_write32(DMA30_BWL_COUNT, val)
+#define bfin_read_DMA30_CURR_BWL_COUNT()	bfin_read32(DMA30_CURR_BWL_COUNT)
+#define bfin_write_DMA30_CURR_BWL_COUNT(val)	bfin_write32(DMA30_CURR_BWL_COUNT, val)
+#define bfin_read_DMA30_BWM_COUNT()		bfin_read32(DMA30_BWM_COUNT)
+#define bfin_write_DMA30_BWM_COUNT(val)		bfin_write32(DMA30_BWM_COUNT, val)
+#define bfin_read_DMA30_CURR_BWM_COUNT()	bfin_read32(DMA30_CURR_BWM_COUNT)
+#define bfin_write_DMA30_CURR_BWM_COUNT(val)	bfin_write32(DMA30_CURR_BWM_COUNT, val)
+
+/* DMA Channel 31 Registers */
+
+#define bfin_read_DMA31_NEXT_DESC_PTR() 	bfin_read32(DMA31_NEXT_DESC_PTR)
+#define bfin_write_DMA31_NEXT_DESC_PTR(val) 	bfin_write32(DMA31_NEXT_DESC_PTR, val)
+#define bfin_read_DMA31_START_ADDR() 		bfin_read32(DMA31_START_ADDR)
+#define bfin_write_DMA31_START_ADDR(val) 	bfin_write32(DMA31_START_ADDR, val)
+#define bfin_read_DMA31_CONFIG()		bfin_read32(DMA31_CONFIG)
+#define bfin_write_DMA31_CONFIG(val)		bfin_write32(DMA31_CONFIG, val)
+#define bfin_read_DMA31_X_COUNT()		bfin_read32(DMA31_X_COUNT)
+#define bfin_write_DMA31_X_COUNT(val)		bfin_write32(DMA31_X_COUNT, val)
+#define bfin_read_DMA31_X_MODIFY()		bfin_read32(DMA31_X_MODIFY)
+#define bfin_write_DMA31_X_MODIFY(val) 		bfin_write32(DMA31_X_MODIFY, val)
+#define bfin_read_DMA31_Y_COUNT()		bfin_read32(DMA31_Y_COUNT)
+#define bfin_write_DMA31_Y_COUNT(val)		bfin_write32(DMA31_Y_COUNT, val)
+#define bfin_read_DMA31_Y_MODIFY()		bfin_read32(DMA31_Y_MODIFY)
+#define bfin_write_DMA31_Y_MODIFY(val) 		bfin_write32(DMA31_Y_MODIFY, val)
+#define bfin_read_DMA31_CURR_DESC_PTR() 	bfin_read32(DMA31_CURR_DESC_PTR)
+#define bfin_write_DMA31_CURR_DESC_PTR(val) 	bfin_write32(DMA31_CURR_DESC_PTR, val)
+#define bfin_read_DMA31_PREV_DESC_PTR() 	bfin_read32(DMA31_PREV_DESC_PTR)
+#define bfin_write_DMA31_PREV_DESC_PTR(val) 	bfin_write32(DMA31_PREV_DESC_PTR, val)
+#define bfin_read_DMA31_CURR_ADDR() 		bfin_read32(DMA31_CURR_ADDR)
+#define bfin_write_DMA31_CURR_ADDR(val) 	bfin_write32(DMA31_CURR_ADDR, val)
+#define bfin_read_DMA31_IRQ_STATUS()		bfin_read32(DMA31_IRQ_STATUS)
+#define bfin_write_DMA31_IRQ_STATUS(val)	bfin_write32(DMA31_IRQ_STATUS, val)
+#define bfin_read_DMA31_CURR_X_COUNT()		bfin_read32(DMA31_CURR_X_COUNT)
+#define bfin_write_DMA31_CURR_X_COUNT(val)	bfin_write32(DMA31_CURR_X_COUNT, val)
+#define bfin_read_DMA31_CURR_Y_COUNT()		bfin_read32(DMA31_CURR_Y_COUNT)
+#define bfin_write_DMA31_CURR_Y_COUNT(val)	bfin_write32(DMA31_CURR_Y_COUNT, val)
+#define bfin_read_DMA31_BWL_COUNT()		bfin_read32(DMA31_BWL_COUNT)
+#define bfin_write_DMA31_BWL_COUNT(val)		bfin_write32(DMA31_BWL_COUNT, val)
+#define bfin_read_DMA31_CURR_BWL_COUNT()	bfin_read32(DMA31_CURR_BWL_COUNT)
+#define bfin_write_DMA31_CURR_BWL_COUNT(val)	bfin_write32(DMA31_CURR_BWL_COUNT, val)
+#define bfin_read_DMA31_BWM_COUNT()		bfin_read32(DMA31_BWM_COUNT)
+#define bfin_write_DMA31_BWM_COUNT(val)		bfin_write32(DMA31_BWM_COUNT, val)
+#define bfin_read_DMA31_CURR_BWM_COUNT()	bfin_read32(DMA31_CURR_BWM_COUNT)
+#define bfin_write_DMA31_CURR_BWM_COUNT(val)	bfin_write32(DMA31_CURR_BWM_COUNT, val)
+
+/* DMA Channel 32 Registers */
+
+#define bfin_read_DMA32_NEXT_DESC_PTR() 	bfin_read32(DMA32_NEXT_DESC_PTR)