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@@ -1356,3 +1356,81 @@
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#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
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#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT)
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#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 30 Registers */
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+
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+#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR)
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+#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR)
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+#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
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+#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG)
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+#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
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+#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT)
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+#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
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+#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY)
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+#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
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+#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT)
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+#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
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+#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY)
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+#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
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+#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR)
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+#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
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+#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR)
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+#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
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+#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR)
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+#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
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+#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS)
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+#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
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+#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT)
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+#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
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+#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT)
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+#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
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+#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT)
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+#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
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+#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT)
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+#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT)
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+#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
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+#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT)
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+#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 31 Registers */
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+
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+#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR)
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+#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR)
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+#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
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+#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG)
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+#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
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+#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT)
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+#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
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+#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY)
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+#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
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+#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT)
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+#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
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+#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY)
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+#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
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+#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR)
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+#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
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+#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR)
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+#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
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+#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR)
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+#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
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+#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS)
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+#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
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+#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT)
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+#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
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+#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT)
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+#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
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+#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT)
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+#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
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+#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT)
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+#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT)
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+#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
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+#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT)
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+#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 32 Registers */
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+
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+#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
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