|
@@ -227,3 +227,129 @@
|
|
#define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012)
|
|
#define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012)
|
|
#define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013)
|
|
#define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013)
|
|
#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014)
|
|
#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014)
|
|
|
|
+#define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015)
|
|
|
|
+#define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016)
|
|
|
|
+#define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017)
|
|
|
|
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018)
|
|
|
|
+
|
|
|
|
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020)
|
|
|
|
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021)
|
|
|
|
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024)
|
|
|
|
+#define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026)
|
|
|
|
+#define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027)
|
|
|
|
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028)
|
|
|
|
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029)
|
|
|
|
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A)
|
|
|
|
+#define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B)
|
|
|
|
+#define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C)
|
|
|
|
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D)
|
|
|
|
+#define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E)
|
|
|
|
+#define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F)
|
|
|
|
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030)
|
|
|
|
+#define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031)
|
|
|
|
+#define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032)
|
|
|
|
+#define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033)
|
|
|
|
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034)
|
|
|
|
+
|
|
|
|
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C)
|
|
|
|
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D)
|
|
|
|
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040)
|
|
|
|
+#define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042)
|
|
|
|
+#define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043)
|
|
|
|
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044)
|
|
|
|
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045)
|
|
|
|
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046)
|
|
|
|
+#define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047)
|
|
|
|
+#define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048)
|
|
|
|
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049)
|
|
|
|
+#define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A)
|
|
|
|
+#define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B)
|
|
|
|
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C)
|
|
|
|
+#define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D)
|
|
|
|
+#define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E)
|
|
|
|
+#define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F)
|
|
|
|
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050)
|
|
|
|
+
|
|
|
|
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058)
|
|
|
|
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059)
|
|
|
|
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C)
|
|
|
|
+#define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E)
|
|
|
|
+#define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F)
|
|
|
|
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060)
|
|
|
|
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061)
|
|
|
|
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062)
|
|
|
|
+#define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063)
|
|
|
|
+#define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064)
|
|
|
|
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065)
|
|
|
|
+#define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066)
|
|
|
|
+#define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067)
|
|
|
|
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068)
|
|
|
|
+#define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069)
|
|
|
|
+#define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A)
|
|
|
|
+#define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B)
|
|
|
|
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C)
|
|
|
|
+
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * Generic GPIO support
|
|
|
|
+ */
|
|
|
|
+#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
|
|
|
|
+#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
|
|
|
|
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
|
|
|
|
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
|
|
|
|
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
|
|
|
|
+
|
|
|
|
+#define MCFGPIO_PIN_MAX 148
|
|
|
|
+#define MCFGPIO_IRQ_MAX 8
|
|
|
|
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * Port Pin Assignment registers.
|
|
|
|
+ */
|
|
|
|
+#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
|
|
|
|
+#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
|
|
|
|
+#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
|
|
|
|
+#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076)
|
|
|
|
+#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
|
|
|
|
+#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
|
|
|
|
+#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A)
|
|
|
|
+#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C)
|
|
|
|
+#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
|
|
|
|
+#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080)
|
|
|
|
+#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
|
|
|
|
+#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
|
|
|
|
+
|
|
|
|
+#define UART0_ENABLE_MASK 0x000f
|
|
|
|
+#define UART1_ENABLE_MASK 0x00f0
|
|
|
|
+#define UART2_ENABLE_MASK 0x3f00
|
|
|
|
+#endif /* CONFIG_M5275 */
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * PIT timer base addresses.
|
|
|
|
+ */
|
|
|
|
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
|
|
|
|
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
|
|
|
|
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
|
|
|
|
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * EPort
|
|
|
|
+ */
|
|
|
|
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
|
|
|
|
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
|
|
|
|
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
|
|
|
|
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
|
|
|
|
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
|
|
|
|
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * Reset Control Unit (relative to IPSBAR).
|
|
|
|
+ */
|
|
|
|
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
|
|
|
|
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
|
|
|
|
+
|
|
|
|
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
|
|
|
|
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
|
|
|
|
+
|
|
|
|
+/****************************************************************************/
|
|
|
|
+#endif /* m527xsim_h */
|