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@@ -228,3 +228,98 @@ extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
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* by introducing sequence points into the in*() definitions. Note that
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* __raw_* do not guarantee this behaviour.
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*
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+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
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+ */
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+#ifdef __io
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+#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
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+#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
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+ cpu_to_le16(v),__io(p)); })
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+#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
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+ cpu_to_le32(v),__io(p)); })
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+
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+#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
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+#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
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+ __raw_readw(__io(p))); __iormb(); __v; })
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+#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
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+ __raw_readl(__io(p))); __iormb(); __v; })
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+
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+#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
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+#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
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+#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
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+
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+#define insb(p,d,l) __raw_readsb(__io(p),d,l)
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+#define insw(p,d,l) __raw_readsw(__io(p),d,l)
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+#define insl(p,d,l) __raw_readsl(__io(p),d,l)
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+#endif
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+
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+#define outb_p(val,port) outb((val),(port))
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+#define outw_p(val,port) outw((val),(port))
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+#define outl_p(val,port) outl((val),(port))
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+#define inb_p(port) inb((port))
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+#define inw_p(port) inw((port))
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+#define inl_p(port) inl((port))
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+
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+#define outsb_p(port,from,len) outsb(port,from,len)
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+#define outsw_p(port,from,len) outsw(port,from,len)
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+#define outsl_p(port,from,len) outsl(port,from,len)
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+#define insb_p(port,to,len) insb(port,to,len)
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+#define insw_p(port,to,len) insw(port,to,len)
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+#define insl_p(port,to,len) insl(port,to,len)
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+
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+/*
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+ * String version of IO memory access ops:
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+ */
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+extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
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+extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
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+extern void _memset_io(volatile void __iomem *, int, size_t);
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+
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+#define mmiowb()
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+
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+/*
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+ * Memory access primitives
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+ * ------------------------
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+ *
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+ * These perform PCI memory accesses via an ioremap region. They don't
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+ * take an address as such, but a cookie.
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+ *
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+ * Again, this are defined to perform little endian accesses. See the
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+ * IO port primitives for more information.
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+ */
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+#ifndef readl
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+#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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+ __raw_readw(c)); __r; })
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+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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+ __raw_readl(c)); __r; })
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+
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+#define writeb_relaxed(v,c) __raw_writeb(v,c)
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+#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
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+#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
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+
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+#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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+#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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+#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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+
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+#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
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+#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
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+#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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+
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+#define readsb(p,d,l) __raw_readsb(p,d,l)
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+#define readsw(p,d,l) __raw_readsw(p,d,l)
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+#define readsl(p,d,l) __raw_readsl(p,d,l)
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+
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+#define writesb(p,d,l) __raw_writesb(p,d,l)
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+#define writesw(p,d,l) __raw_writesw(p,d,l)
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+#define writesl(p,d,l) __raw_writesl(p,d,l)
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+
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+#define memset_io(c,v,l) _memset_io(c,(v),(l))
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+#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
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+#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
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+
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+#endif /* readl */
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+
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+/*
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+ * ioremap and friends.
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+ *
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+ * ioremap takes a PCI memory address, as specified in
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+ * Documentation/io-mapping.txt.
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李欣儒