|
@@ -874,3 +874,100 @@ static pinmux_enum_t pinmux_data[] = {
|
|
|
PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
|
|
|
PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
|
|
|
PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
|
|
|
+ PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
|
|
|
+ PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
|
|
|
+ PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
|
|
|
+ PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
|
|
|
+ PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
|
|
|
+ PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
|
|
|
+ PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
|
|
|
+ PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
|
|
|
+ PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
|
|
|
+ PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
|
|
|
+ PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
|
|
|
+ PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
|
|
|
+ PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
|
|
|
+ PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
|
|
|
+ PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
|
|
|
+ PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
|
|
|
+ PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
|
|
|
+ PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
|
|
|
+ PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
|
|
|
+ PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
|
|
|
+ PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
|
|
|
+ PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
|
|
|
+ PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
|
|
|
+ PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
|
|
|
+ PINMUX_IPSR_DATA(IP3_23, QCLK),
|
|
|
+ PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
|
|
|
+ PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
|
|
|
+ PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
|
|
|
+ PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
|
|
|
+ PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
|
|
|
+ PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
|
|
|
+ PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
|
|
|
+ PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
|
|
|
+ PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
|
|
|
+ PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
|
|
|
+ PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
|
|
|
+ PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
|
|
|
+ PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
|
|
|
+
|
|
|
+ PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
|
|
|
+ PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
|
|
|
+ PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
|
|
|
+ PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
|
|
|
+ PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
|
|
|
+ PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
|
|
|
+ PINMUX_IPSR_DATA(IP4_7_5, PWM6),
|
|
|
+ PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
|
|
|
+ PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
|
|
|
+ PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_10_8, PWM0),
|
|
|
+ PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
|
|
|
+ PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
|
|
|
+ PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
|
|
|
+ PINMUX_IPSR_DATA(IP4_11, VI2_G0),
|
|
|
+ PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
|
|
|
+ PINMUX_IPSR_DATA(IP4_12, VI2_G1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
|
|
|
+ PINMUX_IPSR_DATA(IP4_13, VI2_G2),
|
|
|
+ PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
|
|
|
+ PINMUX_IPSR_DATA(IP4_14, VI2_G3),
|
|
|
+ PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
|
|
|
+ PINMUX_IPSR_DATA(IP4_15, VI2_G4),
|
|
|
+ PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
|
|
|
+ PINMUX_IPSR_DATA(IP4_16, VI2_G5),
|
|
|
+ PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
|
|
|
+ PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
|
|
|
+ PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
|
|
|
+ PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
|
|
|
+ PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
|
|
|
+ PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
|
|
|
+ PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
|