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@@ -3205,3 +3205,14 @@
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/* =========================
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/* =========================
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DPM0
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DPM0
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========================= */
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========================= */
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+#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
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+#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
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+#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
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+#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
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+#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
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+#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
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+#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
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+#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
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+#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
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+#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
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+#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
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