|
|
@@ -195,3 +195,140 @@
|
|
|
|
|
|
#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
|
|
|
#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
|
|
|
+#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
|
|
|
+#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
|
|
|
+#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
|
|
|
+#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
|
|
|
+#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
|
|
|
+#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
|
|
|
+#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
|
|
|
+#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
|
|
|
+
|
|
|
+#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
|
|
|
+#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
|
|
|
+
|
|
|
+/*
|
|
|
+ * Testchip peripheral and fpga gic regions
|
|
|
+ */
|
|
|
+#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
|
|
|
+#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
|
|
|
+
|
|
|
+#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
|
|
|
+#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
|
|
|
+
|
|
|
+#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
|
|
|
+#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
|
|
|
+
|
|
|
+#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
|
|
|
+#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
|
|
|
+
|
|
|
+#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
|
|
|
+#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
|
|
|
+
|
|
|
+/*
|
|
|
+ * Misc block
|
|
|
+ */
|
|
|
+#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
|
|
|
+
|
|
|
+#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
|
|
|
+#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
|
|
|
+#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
|
|
|
+#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
|
|
|
+#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
|
|
|
+#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
|
|
|
+#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
|
|
|
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
|
|
|
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
|
|
|
+#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
|
|
|
+#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
|
|
|
+#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
|
|
|
+#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
|
|
|
+#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
|
|
|
+#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
|
|
|
+#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
|
|
|
+#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
|
|
|
+#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
|
|
|
+#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
|
|
|
+#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
|
|
|
+
|
|
|
+#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
|
|
|
+
|
|
|
+#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
|
|
|
+#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
|
|
|
+#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
|
|
|
+#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
|
|
|
+#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
|
|
|
+#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
|
|
|
+
|
|
|
+#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
|
|
|
+#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
|
|
|
+#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
|
|
|
+#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
|
|
|
+#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
|
|
|
+#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
|
|
|
+
|
|
|
+/*
|
|
|
+ * Power management and clock control
|
|
|
+ */
|
|
|
+#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
|
|
|
+
|
|
|
+#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
|
|
|
+#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
|
|
|
+#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
|
|
|
+#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
|
|
|
+#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
|
|
|
+#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
|
|
|
+#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
|
|
|
+#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
|
|
|
+#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
|
|
|
+#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
|
|
|
+#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
|
|
|
+#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
|
|
|
+#define PM_CSR_REG PMU_MEM_MAP(0x030)
|
|
|
+
|
|
|
+/* PM_CLK_GATE_REG */
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_GPU (24)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_CIM (23)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_LCDC (22)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_I2S (21)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_RAID (20)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_SATA (19)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_TIMER (14)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_HCIE (12)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_GPIO (10)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_UART3 (9)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_UART2 (8)
|
|
|
+#define PM_CLK_GATE_REG_OFFSET_UART1 (7)
|
唐峰