efHotAgingTrendMining memoryCall.h 李欣儒 commit at 2020-12-04

efHotAgingTrendMining/dataSharedMemory/memoryCall.h

@@ -745,3 +745,133 @@
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT				23
 #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH				0x1
 #define OMAP4430_DPLL_BYP_CLKSEL_MASK				(1 << 23)
+
+/* Used by CM_CLKDCOLDO_DPLL_USB */
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT			8
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH			0x1
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK			(1 << 8)
+
+/* Used by CM_CLKSEL_DPLL_CORE */
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT			20
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH			0x1
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK			(1 << 20)
+
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT			0
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH			0x5
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK			(0x1f << 0)
+
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT			5
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH			0x1
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK			(1 << 5)
+
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT			8
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH			0x1
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK			(1 << 8)
+
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT			10
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH			0x1
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK			(1 << 10)
+
+/*
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ */
+#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT				0
+#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH				0x5
+#define OMAP4430_DPLL_CLKOUT_DIV_MASK				(0x1f << 0)
+
+/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT			0
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH			0x7
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK			(0x7f << 0)
+
+/*
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ */
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT			5
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH			0x1
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK			(1 << 5)
+
+/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT		7
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH		0x1
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK		(1 << 7)
+
+/*
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ */
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT			8
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH			0x1
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK			(1 << 8)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT			8
+#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH			0x3
+#define OMAP4430_DPLL_CORE_DPLL_EN_MASK				(0x7 << 8)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT				11
+#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH				0x5
+#define OMAP4430_DPLL_CORE_M2_DIV_MASK				(0x1f << 11)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT				3
+#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH				0x5
+#define OMAP4430_DPLL_CORE_M5_DIV_MASK				(0x1f << 3)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO
+ */
+#define OMAP4430_DPLL_DIV_SHIFT					0
+#define OMAP4430_DPLL_DIV_WIDTH					0x7
+#define OMAP4430_DPLL_DIV_MASK					(0x7f << 0)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_DIV_0_7_SHIFT				0
+#define OMAP4430_DPLL_DIV_0_7_WIDTH				0x8
+#define OMAP4430_DPLL_DIV_0_7_MASK				(0xff << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT			8
+#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH			0x1
+#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK			(1 << 8)
+
+/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT			3
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH			0x1
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK			(1 << 3)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP4430_DPLL_EN_SHIFT					0
+#define OMAP4430_DPLL_EN_WIDTH					0x3
+#define OMAP4430_DPLL_EN_MASK					(0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO
+ */
+#define OMAP4430_DPLL_LPMODE_EN_SHIFT				10
+#define OMAP4430_DPLL_LPMODE_EN_WIDTH				0x1
+#define OMAP4430_DPLL_LPMODE_EN_MASK				(1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO
+ */