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@@ -181,3 +181,29 @@
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#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
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#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
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#define M32R_ICU_CR8_PORTL (0x219+M32R_ICU_OFFSET) /* INT7 */
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+#define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */
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+#define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */
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+#define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */
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+#define M32R_ICU_CR19_PORTL (0x248+M32R_ICU_OFFSET) /* MFT3 */
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+#define M32R_ICU_CR20_PORTL (0x24C+M32R_ICU_OFFSET) /* MFT4 */
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+#define M32R_ICU_CR21_PORTL (0x250+M32R_ICU_OFFSET) /* MFT5 */
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+#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* DMA0 */
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+#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* DMA1 */
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+#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* SIO0 */
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+#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* SIO0 */
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+#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* SIO1 */
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+#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* SIO1 */
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+#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* SIO2 */
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+#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* SIO2 */
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+#define M32R_ICU_CR54_PORTL (0x2D4+M32R_ICU_OFFSET) /* SIO3 */
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+#define M32R_ICU_CR55_PORTL (0x2D8+M32R_ICU_OFFSET) /* SIO3 */
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+#define M32R_ICU_CR56_PORTL (0x2DC+M32R_ICU_OFFSET) /* SIO4 */
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+#define M32R_ICU_CR57_PORTL (0x2E0+M32R_ICU_OFFSET) /* SIO4 */
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+
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+#ifdef CONFIG_SMP
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+#define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET) /* IPI0 */
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+#define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET) /* IPI1 */
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+#define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET) /* IPI2 */
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+#define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET) /* IPI3 */
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+#define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET) /* IPI4 */
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+#define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET) /* IPI5 */
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