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@@ -363,3 +363,142 @@ extern unsigned long get_iop_tick_rate(void);
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#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
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#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
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#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
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#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
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+#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
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+
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+#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
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+#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
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+#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
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+#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
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+#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
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+#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
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+#define IOP13XX_ATUE_OCCAR_REG (2)
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+
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+#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
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+#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
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+#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
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+#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
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+#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
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+#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
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+#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
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+
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+#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
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+#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
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+#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
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+
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+#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
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+#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
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+
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+#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
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+#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
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+#define IOP13XX_ATUE_STAT_PME (1 << 27)
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+#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
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+#define IOP13XX_ATUE_STAT_IVM (1 << 25)
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+#define IOP13XX_ATUE_STAT_BIST (1 << 24)
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+#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
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+#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
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+#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
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+#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
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+#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
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+#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
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+#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
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+#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
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+#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
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+#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
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+#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
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+#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
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+#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
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+#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
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+#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
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+#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
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+#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
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+
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+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
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+#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
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+#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
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+#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
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+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
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+#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
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+#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
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+#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
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+#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
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+#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
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+#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
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+#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
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+#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
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+#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
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+#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
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+
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+#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
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+#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
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+#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
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+#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
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+/*=======================================================================*/
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+
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+/*============================MESSAGING UNIT=============================*/
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+#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
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+ (ofs))
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+
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+#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
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+#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
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+#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
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+#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
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+#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
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+#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
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+#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
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+#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
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+#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
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+#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
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+#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
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+#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
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+#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
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+#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
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+#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
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+#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
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+
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+#define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
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+#define IOP13XX_MU_BASE_PHYS (0xff000000)
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+#define IOP13XX_MU_BASE_PCI (0xff000000)
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+#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
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+#define IOP13XX_MU_MIMR_CORE_SELECT (15)
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+/*=======================================================================*/
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+
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+/*==============================ADMA UNITS===============================*/
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+#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
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+#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
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+
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+/*==============================XSI BRIDGE===============================*/
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+#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
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+#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
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+#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
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+#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
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+ IOP13XX_PMMR_VIRT_TO_PHYS(\
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+ IOP13XX_ATUE_OCCDR))\
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+ && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
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+#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
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+ IOP13XX_PMMR_VIRT_TO_PHYS(\
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+ IOP13XX_ATUX_OCCDR))\
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+ && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
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+/*=======================================================================*/
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+
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+#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
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+ (ofs))
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+
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+#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
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+#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
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+#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
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+#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
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+#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
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+#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
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+
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+#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
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+
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+/* Watchdog timer definitions */
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+#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
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+#define IOP_WDTCR_EN 0xe1e1e1e1
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+#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
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+#define IOP_WDTCR_DIS 0xf1f1f1f1
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+#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
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+#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
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+#define IOP13XX_WDTCR_IB_RESET (1 << 0)
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+
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+#endif /* _IOP13XX_HW_H_ */
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