efElectricAgingTrendMining memoryOperation.h 岳彩东 commit at 2020-11-18

efElectricAgingTrendMining/dataSharedMemory/memoryOperation.h

@@ -1446,3 +1446,184 @@
 #define OMAP4430_VP_CORE_EQVALUE_ST_MASK				(1 << 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT				18
+#define OMAP4430_VP_CORE_MAXVDD_EN_MASK					(1 << 18)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT				18
+#define OMAP4430_VP_CORE_MAXVDD_ST_MASK					(1 << 18)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT				17
+#define OMAP4430_VP_CORE_MINVDD_EN_MASK					(1 << 17)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT				17
+#define OMAP4430_VP_CORE_MINVDD_ST_MASK					(1 << 17)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT				19
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK				(1 << 19)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT				19
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK				(1 << 19)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT				16
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK				(1 << 16)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT				16
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK				(1 << 16)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT				21
+#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK				(1 << 21)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT				21
+#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK				(1 << 21)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT				28
+#define OMAP4430_VP_IVA_EQVALUE_EN_MASK					(1 << 28)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT				28
+#define OMAP4430_VP_IVA_EQVALUE_ST_MASK					(1 << 28)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT					26
+#define OMAP4430_VP_IVA_MAXVDD_EN_MASK					(1 << 26)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT					26
+#define OMAP4430_VP_IVA_MAXVDD_ST_MASK					(1 << 26)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT					25
+#define OMAP4430_VP_IVA_MINVDD_EN_MASK					(1 << 25)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT					25
+#define OMAP4430_VP_IVA_MINVDD_ST_MASK					(1 << 25)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT				27
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK				(1 << 27)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT				27
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK				(1 << 27)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT				24
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK				(1 << 24)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT				24
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK				(1 << 24)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT				29
+#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK				(1 << 29)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT				29
+#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK				(1 << 29)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT				4
+#define OMAP4430_VP_MPU_EQVALUE_EN_MASK					(1 << 4)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT				4
+#define OMAP4430_VP_MPU_EQVALUE_ST_MASK					(1 << 4)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT					2
+#define OMAP4430_VP_MPU_MAXVDD_EN_MASK					(1 << 2)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT					2
+#define OMAP4430_VP_MPU_MAXVDD_ST_MASK					(1 << 2)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT					1
+#define OMAP4430_VP_MPU_MINVDD_EN_MASK					(1 << 1)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT					1
+#define OMAP4430_VP_MPU_MINVDD_ST_MASK					(1 << 1)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT				3
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK				(1 << 3)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT				3
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK				(1 << 3)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT				0
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK				(1 << 0)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT				0
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK				(1 << 0)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT				5
+#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK				(1 << 5)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT				5
+#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK				(1 << 5)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_VSETUPCNT_VALUE_SHIFT					8
+#define OMAP4430_VSETUPCNT_VALUE_MASK					(0xff << 8)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP4430_VSTEPMAX_SHIFT						0
+#define OMAP4430_VSTEPMAX_MASK						(0xff << 0)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP4430_VSTEPMIN_SHIFT						0
+#define OMAP4430_VSTEPMIN_MASK						(0xff << 0)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_WAKE_MODEM_SHIFT					0
+#define OMAP4430_WAKE_MODEM_MASK					(1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT				1
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK				(1 << 1)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT				0
+#define OMAP4430_WKUPDEP_DISPC_MPU_MASK					(1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT				3
+#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK				(1 << 3)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT				2
+#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK				(1 << 2)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT				7
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK				(1 << 7)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT				6
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK				(1 << 6)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT				0
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK				(1 << 0)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT				2