waterInvestigationHiddenDanger analysisDataOperation.c 张婷 commit at 2020-09-14

waterInvestigationHiddenDanger/databaseOperation/analysisDataOperation.c

@@ -82,3 +82,124 @@
 #define PIC_VALID	PIC_VALID_ALL
 #else
 #define IRQ_MMCI0A	IRQ_SIC_MMCI0A
+#define IRQ_AACI	IRQ_SIC_AACI
+#define IRQ_ETH		IRQ_SIC_ETH
+#define PIC_MASK	0
+#define PIC_VALID	PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
+			BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
+			BIT(SIC_INT_ETH)
+#endif
+
+/* Lookup table for finding a DT node that represents the vic instance */
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-vic", },
+	{}
+};
+
+static const struct of_device_id sic_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-sic", },
+	{}
+};
+
+void __init versatile_init_irq(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node_by_address(NULL, vic_of_match,
+					      VERSATILE_VIC_BASE);
+	__vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
+
+	writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
+
+	np = of_find_matching_node_by_address(NULL, sic_of_match,
+					      VERSATILE_SIC_BASE);
+
+	fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
+		IRQ_VICSOURCE31, PIC_VALID, np);
+
+	/*
+	 * Interrupts on secondary controller from 0 to 8 are routed to
+	 * source 31 on PIC.
+	 * Interrupts from 21 to 31 are routed directly to the VIC on
+	 * the corresponding number on primary controller. This is controlled
+	 * by setting PIC_ENABLEx.
+	 */
+	writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
+}
+
+static struct map_desc versatile_io_desc[] __initdata = {
+	{
+		.virtual	=  IO_ADDRESS(VERSATILE_SYS_BASE),
+		.pfn		= __phys_to_pfn(VERSATILE_SYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  IO_ADDRESS(VERSATILE_SIC_BASE),
+		.pfn		= __phys_to_pfn(VERSATILE_SIC_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  IO_ADDRESS(VERSATILE_VIC_BASE),
+		.pfn		= __phys_to_pfn(VERSATILE_VIC_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  IO_ADDRESS(VERSATILE_SCTL_BASE),
+		.pfn		= __phys_to_pfn(VERSATILE_SCTL_BASE),
+		.length		= SZ_4K * 9,
+		.type		= MT_DEVICE
+	},
+#ifdef CONFIG_MACH_VERSATILE_AB
+ 	{
+		.virtual	=  IO_ADDRESS(VERSATILE_IB2_BASE),
+		.pfn		= __phys_to_pfn(VERSATILE_IB2_BASE),
+		.length		= SZ_64M,
+		.type		= MT_DEVICE
+	},
+#endif
+#ifdef CONFIG_DEBUG_LL
+ 	{
+		.virtual	=  IO_ADDRESS(VERSATILE_UART0_BASE),
+		.pfn		= __phys_to_pfn(VERSATILE_UART0_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	},
+#endif
+#ifdef CONFIG_PCI
+ 	{
+		.virtual	=  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
+		.pfn		= __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)VERSATILE_PCI_VIRT_BASE,
+		.pfn		= __phys_to_pfn(VERSATILE_PCI_BASE),
+		.length		= VERSATILE_PCI_BASE_SIZE,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
+		.pfn		= __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
+		.length		= VERSATILE_PCI_CFG_BASE_SIZE,
+		.type		= MT_DEVICE
+	},
+#endif
+};
+
+void __init versatile_map_io(void)
+{
+	iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
+}
+
+
+#define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
+
+static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
+{
+	u32 val;
+
+	val = __raw_readl(VERSATILE_FLASHCTRL);
+	if (on)
+		val |= VERSATILE_FLASHPROG_FLVPPEN;
+	else
+		val &= ~VERSATILE_FLASHPROG_FLVPPEN;
+	__raw_writel(val, VERSATILE_FLASHCTRL);