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+/*
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+ * clkt_clksel.c - OMAP2/3/4 clksel clock functions
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+ *
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+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
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+ * Copyright (C) 2004-2010 Nokia Corporation
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+ *
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+ * Contacts:
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+ * Richard Woodruff <r-woodruff2@ti.com>
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+ * Paul Walmsley
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ *
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+ * clksel clocks are clocks that do not have a fixed parent, or that
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+ * can divide their parent's rate, or possibly both at the same time, based
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+ * on the contents of a hardware register bitfield.
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+ *
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+ * All of the various mux and divider settings can be encoded into
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+ * struct clksel* data structures, and then these can be autogenerated
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+ * from some hardware database for each new chip generation. This
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+ * should avoid the need to write, review, and validate a lot of new
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+ * clock code for each new chip, since it can be exported from the SoC
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+ * design flow. This is now done on OMAP4.
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+ *
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+ * The fusion of mux and divider clocks is a software creation. In
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+ * hardware reality, the multiplexer (parent selection) and the
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+ * divider exist separately. XXX At some point these clksel clocks
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+ * should be split into "divider" clocks and "mux" clocks to better
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+ * match the hardware.
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+ *
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+ * (The name "clksel" comes from the name of the corresponding
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+ * register field in the OMAP2/3 family of SoCs.)
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+ *
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+ * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
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+ * many of the OMAP1 clocks should be convertible to use this
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+ * mechanism.
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+ */
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+#undef DEBUG
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+
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+#include <linux/kernel.h>
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+#include <linux/errno.h>
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+#include <linux/clk-provider.h>
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+#include <linux/io.h>
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+#include <linux/bug.h>
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+
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+#include "clock.h"
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+
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+/* Private functions */
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+
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+/**
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+ * _get_clksel_by_parent() - return clksel struct for a given clk & parent
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+ * @clk: OMAP struct clk ptr to inspect
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+ * @src_clk: OMAP struct clk ptr of the parent clk to search for
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+ *
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+ * Scan the struct clksel array associated with the clock to find
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+ * the element associated with the supplied parent clock address.
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+ * Returns a pointer to the struct clksel on success or NULL on error.
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+ */
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+static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk,
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+ struct clk *src_clk)
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+{
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+ const struct clksel *clks;
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+
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+ if (!src_clk)
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+ return NULL;
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+
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+ for (clks = clk->clksel; clks->parent; clks++)
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+ if (clks->parent == src_clk)
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+ break; /* Found the requested parent */
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+
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+ if (!clks->parent) {
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+ /* This indicates a data problem */
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+ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
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+ __clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
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+ return NULL;
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+ }
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+
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+ return clks;
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+}
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+
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+/**
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+ * _write_clksel_reg() - program a clock's clksel register in hardware
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+ * @clk: struct clk * to program
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+ * @v: clksel bitfield value to program (with LSB at bit 0)
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+ *
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+ * Shift the clksel register bitfield value @v to its appropriate
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+ * location in the clksel register and write it in. This function
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+ * will ensure that the write to the clksel_reg reaches its
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+ * destination before returning -- important since PRM and CM register
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+ * accesses can be quite slow compared to ARM cycles -- but does not
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宁志军