efDataStatistics memoryOperation.h 张婷 commit at 2021-01-11

efDataStatistics/dataSharedMemory/memoryOperation.h

@@ -0,0 +1,116 @@
+/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8X60_H
+#define __ASM_ARCH_MSM_IRQS_8X60_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 0)
+#define INT_GP_TIMER_EXP			(GIC_PPI_START + 1)
+#define INT_GP_TIMER2_EXP			(GIC_PPI_START + 2)
+#define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 3)
+#define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
+#define AVS_SVICINT				(GIC_PPI_START + 5)
+#define AVS_SVICINTSWDONE			(GIC_PPI_START + 6)
+#define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 8)
+#define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 9)
+#define SC_AVSCPUXDOWN				(GIC_PPI_START + 10)
+#define SC_AVSCPUXUP				(GIC_PPI_START + 11)
+#define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 12)
+/* PPI 13 to 15 are unused */
+
+
+#define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
+#define SC_SICL2ACGIRPTREQ			(GIC_SPI_START + 2)
+#define NC					(GIC_SPI_START + 3)
+#define TLMM_SCSS_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
+#define TLMM_SCSS_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
+#define TLMM_SCSS_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
+#define TLMM_SCSS_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
+#define TLMM_SCSS_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
+#define TLMM_SCSS_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
+#define TLMM_SCSS_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
+#define TLMM_SCSS_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
+#define TLMM_SCSS_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
+#define TLMM_SCSS_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
+#define PM8058_SEC_IRQ_N			(GIC_SPI_START + 14)
+#define PM8901_SEC_IRQ_N			(GIC_SPI_START + 15)
+#define TLMM_SCSS_SUMMARY_IRQ			(GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
+#define RPM_SCSS_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
+#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
+#define RPM_SCSS_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
+#define RPM_SCSS_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
+#define RPM_SCSS_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
+#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
+#define RPM_SCSS_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
+#define RPM_SCSS_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_INT		(GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_INT		(GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_INT		(GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_INT		(GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
+#define MARM_FIQ				(GIC_SPI_START + 33)
+#define MARM_IRQ				(GIC_SPI_START + 34)
+#define MARM_L2CC_IRQ				(GIC_SPI_START + 35)
+#define MARM_WDOG_EXPIRED			(GIC_SPI_START + 36)
+#define MARM_SCSS_GP_IRQ_0			(GIC_SPI_START + 37)
+#define MARM_SCSS_GP_IRQ_1			(GIC_SPI_START + 38)
+#define MARM_SCSS_GP_IRQ_2			(GIC_SPI_START + 39)
+#define MARM_SCSS_GP_IRQ_3			(GIC_SPI_START + 40)
+#define MARM_SCSS_GP_IRQ_4			(GIC_SPI_START + 41)
+#define MARM_SCSS_GP_IRQ_5			(GIC_SPI_START + 42)
+#define MARM_SCSS_GP_IRQ_6			(GIC_SPI_START + 43)
+#define MARM_SCSS_GP_IRQ_7			(GIC_SPI_START + 44)
+#define MARM_SCSS_GP_IRQ_8			(GIC_SPI_START + 45)
+#define MARM_SCSS_GP_IRQ_9			(GIC_SPI_START + 46)
+#define VPE_IRQ					(GIC_SPI_START + 47)
+#define VFE_IRQ					(GIC_SPI_START + 48)
+#define VCODEC_IRQ				(GIC_SPI_START + 49)
+#define TV_ENC_IRQ				(GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
+#define ROT_IRQ					(GIC_SPI_START + 73)