|
|
@@ -0,0 +1,88 @@
|
|
|
+/*
|
|
|
+ * arch/arm/include/asm/io.h
|
|
|
+ *
|
|
|
+ * Copyright (C) 1996-2000 Russell King
|
|
|
+ *
|
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
|
+ * published by the Free Software Foundation.
|
|
|
+ *
|
|
|
+ * Modifications:
|
|
|
+ * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
|
|
|
+ * constant addresses and variable addresses.
|
|
|
+ * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
|
|
|
+ * specific IO header files.
|
|
|
+ * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
|
|
|
+ * 04-Apr-1999 PJB Added check_signature.
|
|
|
+ * 12-Dec-1999 RMK More cleanups
|
|
|
+ * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
|
|
|
+ * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
|
|
|
+ */
|
|
|
+#ifndef __ASM_ARM_IO_H
|
|
|
+#define __ASM_ARM_IO_H
|
|
|
+
|
|
|
+#ifdef __KERNEL__
|
|
|
+
|
|
|
+#include <linux/types.h>
|
|
|
+#include <asm/byteorder.h>
|
|
|
+#include <asm/memory.h>
|
|
|
+#include <asm-generic/pci_iomap.h>
|
|
|
+
|
|
|
+/*
|
|
|
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
|
|
|
+ */
|
|
|
+#define isa_virt_to_bus virt_to_phys
|
|
|
+#define isa_page_to_bus page_to_phys
|
|
|
+#define isa_bus_to_virt phys_to_virt
|
|
|
+
|
|
|
+/*
|
|
|
+ * Generic IO read/write. These perform native-endian accesses. Note
|
|
|
+ * that some architectures will want to re-define __raw_{read,write}w.
|
|
|
+ */
|
|
|
+extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
|
|
|
+extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
|
|
|
+extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
|
|
|
+
|
|
|
+extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
|
|
|
+extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
|
|
|
+extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
|
|
|
+
|
|
|
+#if __LINUX_ARM_ARCH__ < 6
|
|
|
+/*
|
|
|
+ * Half-word accesses are problematic with RiscPC due to limitations of
|
|
|
+ * the bus. Rather than special-case the machine, just let the compiler
|
|
|
+ * generate the access for CPUs prior to ARMv6.
|
|
|
+ */
|
|
|
+#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
|
|
|
+#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
|
|
|
+#else
|
|
|
+/*
|
|
|
+ * When running under a hypervisor, we want to avoid I/O accesses with
|
|
|
+ * writeback addressing modes as these incur a significant performance
|
|
|
+ * overhead (the address generation must be emulated in software).
|
|
|
+ */
|
|
|
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ asm volatile("strh %1, %0"
|
|
|
+ : "+Q" (*(volatile u16 __force *)addr)
|
|
|
+ : "r" (val));
|
|
|
+}
|
|
|
+
|
|
|
+static inline u16 __raw_readw(const volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ u16 val;
|
|
|
+ asm volatile("ldrh %1, %0"
|
|
|
+ : "+Q" (*(volatile u16 __force *)addr),
|
|
|
+ "=r" (val));
|
|
|
+ return val;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
|
|
|
+{
|
|
|
+ asm volatile("strb %1, %0"
|
|
|
+ : "+Qo" (*(volatile u8 __force *)addr)
|
|
|
+ : "r" (val));
|
|
|
+}
|
|
|
+
|
|
|
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
|
李欣儒