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@@ -879,3 +879,84 @@
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#define DLENGTH 0x00003800 /* PPI Data Length */
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#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
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#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
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+#define DLEN_10 0x00000800 /* Data Length = 10 Bits */
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+#define DLEN_11 0x00001000 /* Data Length = 11 Bits */
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+#define DLEN_12 0x00001800 /* Data Length = 12 Bits */
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+#define DLEN_13 0x00002000 /* Data Length = 13 Bits */
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+#define DLEN_14 0x00002800 /* Data Length = 14 Bits */
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+#define DLEN_15 0x00003000 /* Data Length = 15 Bits */
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+#define DLEN_16 0x00003800 /* Data Length = 16 Bits */
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+#define POL 0x0000C000 /* PPI Signal Polarities */
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+#define POLC 0x4000 /* PPI Clock Polarity */
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+#define POLS 0x8000 /* PPI Frame Sync Polarity */
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+
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+/* PPI_STATUS Masks */
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+#define FLD 0x00000400 /* Field Indicator */
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+#define FT_ERR 0x00000800 /* Frame Track Error */
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+#define OVR 0x00001000 /* FIFO Overflow Error */
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+#define UNDR 0x00002000 /* FIFO Underrun Error */
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+#define ERR_DET 0x00004000 /* Error Detected Indicator */
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+#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
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+
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+/* ********** DMA CONTROLLER MASKS *********************8 */
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+
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+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
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+
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+#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
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+#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
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+#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
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+#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
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+#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
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+#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
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+#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
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+#define PMAP 0x00007000 /* DMA Peripheral Map Field */
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+
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+/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
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+
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+/* PWM Timer bit definitions */
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+
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+/* TIMER_ENABLE Register */
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+#define TIMEN0 0x0001
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+#define TIMEN1 0x0002
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+#define TIMEN2 0x0004
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+#define TIMEN3 0x0008
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+#define TIMEN4 0x0010
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+#define TIMEN5 0x0020
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+#define TIMEN6 0x0040
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+#define TIMEN7 0x0080
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+#define TIMEN8 0x0001
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+#define TIMEN9 0x0002
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+#define TIMEN10 0x0004
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+#define TIMEN11 0x0008
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+
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+#define TIMEN0_P 0x00
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+#define TIMEN1_P 0x01
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+#define TIMEN2_P 0x02
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+#define TIMEN3_P 0x03
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+#define TIMEN4_P 0x04
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+#define TIMEN5_P 0x05
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+#define TIMEN6_P 0x06
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+#define TIMEN7_P 0x07
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+#define TIMEN8_P 0x00
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+#define TIMEN9_P 0x01
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+#define TIMEN10_P 0x02
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+#define TIMEN11_P 0x03
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+
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+/* TIMER_DISABLE Register */
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+#define TIMDIS0 0x0001
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+#define TIMDIS1 0x0002
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+#define TIMDIS2 0x0004
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+#define TIMDIS3 0x0008
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+#define TIMDIS4 0x0010
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+#define TIMDIS5 0x0020
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+#define TIMDIS6 0x0040
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+#define TIMDIS7 0x0080
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+#define TIMDIS8 0x0001
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+#define TIMDIS9 0x0002
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+#define TIMDIS10 0x0004
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+#define TIMDIS11 0x0008
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+
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+#define TIMDIS0_P 0x00
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+#define TIMDIS1_P 0x01
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+#define TIMDIS2_P 0x02
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+#define TIMDIS3_P 0x03
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