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@@ -0,0 +1,84 @@
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+/*
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+ * OMAP4 Clock data
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+ *
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+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
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+ * Copyright (C) 2009-2010 Nokia Corporation
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+ *
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+ * Paul Walmsley (paul@pwsan.com)
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+ * Rajendra Nayak (rnayak@ti.com)
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+ * Benoit Cousson (b-cousson@ti.com)
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+ * Mike Turquette (mturquette@ti.com)
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * XXX Some of the ES1 clocks have been removed/changed; once support
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+ * is added for discriminating clocks by ES level, these should be added back
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+ * in.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/list.h>
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+#include <linux/clk-private.h>
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+#include <linux/clkdev.h>
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+#include <linux/io.h>
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+
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+#include "soc.h"
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+#include "iomap.h"
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+#include "clock.h"
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+#include "clock44xx.h"
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+#include "cm1_44xx.h"
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+#include "cm2_44xx.h"
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+#include "cm-regbits-44xx.h"
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+#include "prm44xx.h"
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+#include "prm-regbits-44xx.h"
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+#include "control.h"
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+#include "scrm44xx.h"
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+
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+/* OMAP4 modulemode control */
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+#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
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+#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
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+
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+/*
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+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
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+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
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+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
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+ * half of this value.
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+ */
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+#define OMAP4_DPLL_ABE_DEFFREQ 98304000
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+
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+/* Root clocks */
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+
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+DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
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+
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+DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
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+ OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
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+ 0x0, NULL);
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+
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+DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
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+
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+DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
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+ OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
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+ 0x0, NULL);
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+
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+DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
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+
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李欣儒