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@@ -1198,3 +1198,107 @@
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#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
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#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
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#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
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+#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
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+#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
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+#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
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+
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+
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+/* ********************************************************** */
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+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
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+/* and MULTI BIT READ MACROS */
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+/* ********************************************************** */
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+
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+/* Bit masks for HOST_CONTROL */
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+
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+#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
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+#define HOST_CNTR_nHOST_EN 0x0
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+#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
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+#define HOST_CNTR_nHOST_END 0x0
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+#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
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+#define HOST_CNTR_nDATA_SIZE 0x0
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+#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
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+#define HOST_CNTR_nHOST_RST 0x0
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+#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
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+#define HOST_CNTR_nHRDY_OVR 0x0
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+#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
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+#define HOST_CNTR_nINT_MODE 0x0
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+#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
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+#define HOST_CNTR_ nBT_EN 0x0
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+#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
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+#define HOST_CNTR_nEHW 0x0
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+#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
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+#define HOST_CNTR_nEHR 0x0
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+#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
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+#define HOST_CNTR_nBDR 0x0
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+
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+/* Bit masks for HOST_STATUS */
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+
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+#define HOST_STAT_READY 0x1 /* DMA Ready */
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+#define HOST_STAT_nREADY 0x0
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+#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
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+#define HOST_STAT_nFIFOFULL 0x0
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+#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
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+#define HOST_STAT_nFIFOEMPTY 0x0
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+#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
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+#define HOST_STAT_nCOMPLETE 0x0
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+#define HOST_STAT_HSHK 0x10 /* Host Handshake */
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+#define HOST_STAT_nHSHK 0x0
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+#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
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+#define HOST_STAT_nTIMEOUT 0x0
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+#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
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+#define HOST_STAT_nHIRQ 0x0
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+#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
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+#define HOST_STAT_nALLOW_CNFG 0x0
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+#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
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+#define HOST_STAT_nDMA_DIR 0x0
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+#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
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+#define HOST_STAT_nBTE 0x0
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+#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
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+#define HOST_STAT_nHOSTRD_DONE 0x0
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+
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+/* Bit masks for HOST_TIMEOUT */
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+
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+#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
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+
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+/* Bit masks for SECURE_SYSSWT */
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+
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+#define EMUDABL 0x1 /* Emulation Disable. */
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+#define nEMUDABL 0x0
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+#define RSTDABL 0x2 /* Reset Disable */
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+#define nRSTDABL 0x0
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+#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
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+#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
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+#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
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+#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
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+#define nDMA0OVR 0x0
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+#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
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+#define nDMA1OVR 0x0
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+#define EMUOVR 0x4000 /* Emulation Override */
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+#define nEMUOVR 0x0
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+#define OTPSEN 0x8000 /* OTP Secrets Enable. */
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+#define nOTPSEN 0x0
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+#define L2DABL 0x70000 /* L2 Memory Disable. */
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+
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+/* Bit masks for SECURE_CONTROL */
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+
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+#define SECURE0 0x1 /* SECURE 0 */
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+#define nSECURE0 0x0
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+#define SECURE1 0x2 /* SECURE 1 */
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+#define nSECURE1 0x0
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+#define SECURE2 0x4 /* SECURE 2 */
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+#define nSECURE2 0x0
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+#define SECURE3 0x8 /* SECURE 3 */
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+#define nSECURE3 0x0
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+
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+/* Bit masks for SECURE_STATUS */
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+
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+#define SECMODE 0x3 /* Secured Mode Control State */
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+#define NMI 0x4 /* Non Maskable Interrupt */
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+#define nNMI 0x0
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+#define AFVALID 0x8 /* Authentication Firmware Valid */
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+#define nAFVALID 0x0
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+#define AFEXIT 0x10 /* Authentication Firmware Exit */
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+#define nAFEXIT 0x0
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+#define SECSTAT 0xe0 /* Secure Status */
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+
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+#endif /* _DEF_BF512_H */
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