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@@ -1076,3 +1076,64 @@ marvel_agp_info(void)
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for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) {
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struct pci_controller *h;
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vuip addr;
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+
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+ if (!io7->ports[IO7_AGP_PORT].enabled)
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+ continue;
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+
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+ h = io7->ports[IO7_AGP_PORT].hose;
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+ addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0);
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+
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+ if (*addr != 0xffffffffu) {
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+ hose = h;
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+ break;
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+ }
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+ }
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+
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+ if (!hose || !hose->sg_pci)
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+ return NULL;
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+
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+ printk("MARVEL - using hose %d as AGP\n", hose->index);
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+
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+ /*
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+ * Get the csrs from the hose.
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+ */
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+ csrs = ((struct io7_port *)hose->sysdata)->csrs;
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+
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+ /*
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+ * Allocate the info structure.
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+ */
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+ agp = kmalloc(sizeof(*agp), GFP_KERNEL);
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+ if (!agp)
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+ return NULL;
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+
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+ /*
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+ * Fill it in.
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+ */
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+ agp->hose = hose;
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+ agp->private = NULL;
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+ agp->ops = &marvel_agp_ops;
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+
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+ /*
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+ * Aperture - not configured until ops.setup().
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+ */
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+ agp->aperture.bus_base = 0;
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+ agp->aperture.size = 0;
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+ agp->aperture.sysdata = NULL;
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+
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+ /*
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+ * Capabilities.
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+ *
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+ * NOTE: IO7 reports through AGP_STAT that it can support a read queue
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+ * depth of 17 (rq = 0x10). It actually only supports a depth of
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+ * 16 (rq = 0xf).
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+ */
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+ agp->capability.lw = csrs->AGP_STAT.csr;
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+ agp->capability.bits.rq = 0xf;
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+
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+ /*
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+ * Mode.
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+ */
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+ agp->mode.lw = csrs->AGP_CMD.csr;
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+
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+ return agp;
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+}
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