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@@ -531,3 +531,173 @@ typedef struct scc_enet {
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/* SCC Mode Register (PMSR) as used by Ethernet.
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*/
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#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
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+#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
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+#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
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+#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
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+#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
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+#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
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+#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
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+#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
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+#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
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+#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
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+#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
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+#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
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+#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
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+
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+/* Buffer descriptor control/status used by Ethernet receive.
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+*/
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+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
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+#define BD_ENET_RX_WRAP ((ushort)0x2000)
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+#define BD_ENET_RX_INTR ((ushort)0x1000)
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+#define BD_ENET_RX_LAST ((ushort)0x0800)
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+#define BD_ENET_RX_FIRST ((ushort)0x0400)
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+#define BD_ENET_RX_MISS ((ushort)0x0100)
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+#define BD_ENET_RX_LG ((ushort)0x0020)
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+#define BD_ENET_RX_NO ((ushort)0x0010)
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+#define BD_ENET_RX_SH ((ushort)0x0008)
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+#define BD_ENET_RX_CR ((ushort)0x0004)
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+#define BD_ENET_RX_OV ((ushort)0x0002)
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+#define BD_ENET_RX_CL ((ushort)0x0001)
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+#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
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+
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+/* Buffer descriptor control/status used by Ethernet transmit.
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+*/
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+#define BD_ENET_TX_READY ((ushort)0x8000)
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+#define BD_ENET_TX_PAD ((ushort)0x4000)
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+#define BD_ENET_TX_WRAP ((ushort)0x2000)
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+#define BD_ENET_TX_INTR ((ushort)0x1000)
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+#define BD_ENET_TX_LAST ((ushort)0x0800)
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+#define BD_ENET_TX_TC ((ushort)0x0400)
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+#define BD_ENET_TX_DEF ((ushort)0x0200)
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+#define BD_ENET_TX_HB ((ushort)0x0100)
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+#define BD_ENET_TX_LC ((ushort)0x0080)
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+#define BD_ENET_TX_RL ((ushort)0x0040)
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+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
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+#define BD_ENET_TX_UN ((ushort)0x0002)
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+#define BD_ENET_TX_CSL ((ushort)0x0001)
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+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
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+
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+/* SCC as UART
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+*/
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+typedef struct scc_uart {
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+ sccp_t scc_genscc;
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+ uint scc_res1; /* Reserved */
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+ uint scc_res2; /* Reserved */
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+ ushort scc_maxidl; /* Maximum idle chars */
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+ ushort scc_idlc; /* temp idle counter */
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+ ushort scc_brkcr; /* Break count register */
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+ ushort scc_parec; /* receive parity error counter */
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+ ushort scc_frmec; /* receive framing error counter */
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+ ushort scc_nosec; /* receive noise counter */
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+ ushort scc_brkec; /* receive break condition counter */
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+ ushort scc_brkln; /* last received break length */
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+ ushort scc_uaddr1; /* UART address character 1 */
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+ ushort scc_uaddr2; /* UART address character 2 */
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+ ushort scc_rtemp; /* Temp storage */
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+ ushort scc_toseq; /* Transmit out of sequence char */
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+ ushort scc_char1; /* control character 1 */
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+ ushort scc_char2; /* control character 2 */
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+ ushort scc_char3; /* control character 3 */
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+ ushort scc_char4; /* control character 4 */
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+ ushort scc_char5; /* control character 5 */
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+ ushort scc_char6; /* control character 6 */
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+ ushort scc_char7; /* control character 7 */
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+ ushort scc_char8; /* control character 8 */
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+ ushort scc_rccm; /* receive control character mask */
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+ ushort scc_rccr; /* receive control character register */
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+ ushort scc_rlbc; /* receive last break character */
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+} scc_uart_t;
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+
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+/* SCC Event and Mask registers when it is used as a UART.
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+*/
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+#define UART_SCCM_GLR ((ushort)0x1000)
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+#define UART_SCCM_GLT ((ushort)0x0800)
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+#define UART_SCCM_AB ((ushort)0x0200)
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+#define UART_SCCM_IDL ((ushort)0x0100)
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+#define UART_SCCM_GRA ((ushort)0x0080)
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+#define UART_SCCM_BRKE ((ushort)0x0040)
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+#define UART_SCCM_BRKS ((ushort)0x0020)
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+#define UART_SCCM_CCR ((ushort)0x0008)
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+#define UART_SCCM_BSY ((ushort)0x0004)
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+#define UART_SCCM_TX ((ushort)0x0002)
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+#define UART_SCCM_RX ((ushort)0x0001)
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+
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+/* The SCC PMSR when used as a UART.
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+*/
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+#define SCU_PMSR_FLC ((ushort)0x8000)
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+#define SCU_PMSR_SL ((ushort)0x4000)
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+#define SCU_PMSR_CL ((ushort)0x3000)
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+#define SCU_PMSR_UM ((ushort)0x0c00)
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+#define SCU_PMSR_FRZ ((ushort)0x0200)
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+#define SCU_PMSR_RZS ((ushort)0x0100)
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+#define SCU_PMSR_SYN ((ushort)0x0080)
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+#define SCU_PMSR_DRT ((ushort)0x0040)
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+#define SCU_PMSR_PEN ((ushort)0x0010)
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+#define SCU_PMSR_RPM ((ushort)0x000c)
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+#define SCU_PMSR_REVP ((ushort)0x0008)
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+#define SCU_PMSR_TPM ((ushort)0x0003)
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+#define SCU_PMSR_TEVP ((ushort)0x0003)
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+
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+/* CPM Transparent mode SCC.
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+ */
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+typedef struct scc_trans {
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+ sccp_t st_genscc;
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+ uint st_cpres; /* Preset CRC */
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+ uint st_cmask; /* Constant mask for CRC */
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+} scc_trans_t;
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+
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+#define BD_SCC_TX_LAST ((ushort)0x0800)
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+
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+
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+
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+/* CPM interrupts. There are nearly 32 interrupts generated by CPM
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+ * channels or devices. All of these are presented to the PPC core
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+ * as a single interrupt. The CPM interrupt handler dispatches its
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+ * own handlers, in a similar fashion to the PPC core handler. We
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+ * use the table as defined in the manuals (i.e. no special high
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+ * priority and SCC1 == SCCa, etc...).
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+ */
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+/* #define CPMVEC_NR 32 */
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+/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
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+/* #define CPMVEC_SCC1 ((ushort)0x1e) */
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+/* #define CPMVEC_SCC2 ((ushort)0x1d) */
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+/* #define CPMVEC_SCC3 ((ushort)0x1c) */
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+/* #define CPMVEC_SCC4 ((ushort)0x1b) */
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+/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
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+/* #define CPMVEC_TIMER1 ((ushort)0x19) */
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+/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
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+/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
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+/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
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+/* #define CPMVEC_IDMA1 ((ushort)0x15) */
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+/* #define CPMVEC_IDMA2 ((ushort)0x14) */
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+/* #define CPMVEC_TIMER2 ((ushort)0x12) */
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+/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
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+/* #define CPMVEC_I2C ((ushort)0x10) */
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+/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
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+/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
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+/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
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+/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
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+/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
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+/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
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+/* #define CPMVEC_TIMER4 ((ushort)0x07) */
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+/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
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+/* #define CPMVEC_SPI ((ushort)0x05) */
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+/* #define CPMVEC_SMC1 ((ushort)0x04) */
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+/* #define CPMVEC_SMC2 ((ushort)0x03) */
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+/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
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+/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
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+/* #define CPMVEC_ERROR ((ushort)0x00) */
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+
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+extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
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+
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+/* CPM interrupt configuration vector.
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+*/
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+#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
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+#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
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+#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
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+#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
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+#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
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+#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
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+#define CICR_IEN ((uint)0x00000080) /* Int. enable */
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+#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
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+#endif /* __CPM_360__ */
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吉超博