|
|
@@ -542,3 +542,107 @@
|
|
|
#define PK(x) (1 << (x))
|
|
|
|
|
|
#define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
|
|
|
+#define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
|
|
|
+#define PK_R_W 0x02 /* Use R/W as PK[1] */
|
|
|
+#define PK_LDS 0x04 /* Use /LDS as PK[2] */
|
|
|
+#define PK_UDS 0x08 /* Use /UDS as PK[3] */
|
|
|
+#define PK_LD4 0x10 /* Use LD4 as PK[4] */
|
|
|
+#define PK_LD5 0x20 /* Use LD5 as PK[5] */
|
|
|
+#define PK_LD6 0x40 /* Use LD6 as PK[6] */
|
|
|
+#define PK_LD7 0x80 /* Use LD7 as PK[7] */
|
|
|
+
|
|
|
+#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
|
|
|
+#define PJDATA_ADDR 0xfffff439 /* Port J data register */
|
|
|
+#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
|
|
|
+#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
|
|
|
+
|
|
|
+#define PJDIR BYTE_REF(PJDIR_ADDR)
|
|
|
+#define PJDATA BYTE_REF(PJDATA_ADDR)
|
|
|
+#define PJPUEN BYTE_REF(PJPUEN_ADDR)
|
|
|
+#define PJSEL BYTE_REF(PJSEL_ADDR)
|
|
|
+
|
|
|
+#define PJ(x) (1 << (x))
|
|
|
+
|
|
|
+#define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
|
|
|
+#define PJ_MISO 0x02 /* Use MISO as PJ[1] */
|
|
|
+#define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
|
|
|
+#define PJ_SS 0x08 /* Use SS as PJ[3] */
|
|
|
+#define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
|
|
|
+#define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
|
|
|
+#define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
|
|
|
+#define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Port M
|
|
|
+ */
|
|
|
+#define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
|
|
|
+#define PMDATA_ADDR 0xfffff449 /* Port M data register */
|
|
|
+#define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
|
|
|
+#define PMSEL_ADDR 0xfffff44b /* Port M Select Register */
|
|
|
+
|
|
|
+#define PMDIR BYTE_REF(PMDIR_ADDR)
|
|
|
+#define PMDATA BYTE_REF(PMDATA_ADDR)
|
|
|
+#define PMPUEN BYTE_REF(PMPUEN_ADDR)
|
|
|
+#define PMSEL BYTE_REF(PMSEL_ADDR)
|
|
|
+
|
|
|
+#define PM(x) (1 << (x))
|
|
|
+
|
|
|
+#define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
|
|
|
+#define PM_SDCE 0x02 /* Use SDCE as PM[1] */
|
|
|
+#define PM_DQMH 0x04 /* Use DQMH as PM[2] */
|
|
|
+#define PM_DQML 0x08 /* Use DQML as PM[3] */
|
|
|
+#define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
|
|
|
+#define PM_DMOE 0x20 /* Use DMOE as PM[5] */
|
|
|
+
|
|
|
+/**********
|
|
|
+ *
|
|
|
+ * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
|
|
|
+ *
|
|
|
+ **********/
|
|
|
+
|
|
|
+/*
|
|
|
+ * PWM Control Register
|
|
|
+ */
|
|
|
+#define PWMC_ADDR 0xfffff500
|
|
|
+#define PWMC WORD_REF(PWMC_ADDR)
|
|
|
+
|
|
|
+#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
|
|
|
+#define PWMC_CLKSEL_SHIFT 0
|
|
|
+#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
|
|
|
+#define PWMC_REPEAT_SHIFT 2
|
|
|
+#define PWMC_EN 0x0010 /* Enable PWM */
|
|
|
+#define PMNC_FIFOAV 0x0020 /* FIFO Available */
|
|
|
+#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
|
|
|
+#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
|
|
|
+#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
|
|
|
+#define PWMC_PRESCALER_SHIFT 8
|
|
|
+#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
|
|
|
+
|
|
|
+/* '328-compatible definitions */
|
|
|
+#define PWMC_PWMEN PWMC_EN
|
|
|
+
|
|
|
+/*
|
|
|
+ * PWM Sample Register
|
|
|
+ */
|
|
|
+#define PWMS_ADDR 0xfffff502
|
|
|
+#define PWMS WORD_REF(PWMS_ADDR)
|
|
|
+
|
|
|
+/*
|
|
|
+ * PWM Period Register
|
|
|
+ */
|
|
|
+#define PWMP_ADDR 0xfffff504
|
|
|
+#define PWMP BYTE_REF(PWMP_ADDR)
|
|
|
+
|
|
|
+/*
|
|
|
+ * PWM Counter Register
|
|
|
+ */
|
|
|
+#define PWMCNT_ADDR 0xfffff505
|
|
|
+#define PWMCNT BYTE_REF(PWMCNT_ADDR)
|
|
|
+
|
|
|
+/**********
|
|
|
+ *
|
|
|
+ * 0xFFFFF6xx -- General-Purpose Timer
|
|
|
+ *
|
|
|
+ **********/
|
|
|
+
|
|
|
+/*
|
